[M] Change in coreboot[main]: soc/intel/xeon_sp: Create CXL domains

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81099?usp=email )

Change subject: soc/intel/xeon_sp: Create CXL domains
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Patch Set 5:

(1 comment)

File src/soc/intel/xeon_sp/chip_common.c:

https://review.coreboot.org/c/coreboot/+/81099/comment/13fd4df1_6abdc0a5 :
PS4, Line 274: BusBase
> > From what I understand looking that the Intel reference code the PCI domain always covers all buss […]

Both bridges are all enumerable bridges by generic PCI codes.
The PCI bridge only contains RCiEP.
The CXL bridge only contains CXL 1.0 end-points.