Change in coreboot[master]: soc/intel/common: Add Raptor Lake device IDs

[Bora Guvendik (Code Review)]

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63750 )

Change subject: soc/intel/common: Add Raptor Lake device IDs
......................................................................

soc/intel/common: Add Raptor Lake device IDs

Add Raptor Lake specific CPU, System Agent, PCH,
IGD device IDs.

Document Number: 640555, 626817

Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba
Signed-off-by: Bora Guvendik 
---
M src/include/cpu/intel/cpu_ids.h
M src/include/device/pci_ids.h
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/include/soc/cpu.h
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/dtt/dtt.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/ipu/ipu.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/common/block/usb4/xhci.c
14 files changed, 51 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/63750/1

diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index 6d36851..aafdc3e 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -59,4 +59,6 @@
 #define CPUID_ALDERLAKE_N_A0		0xb06e0
 #define CPUID_METEORLAKE_A0_1		0xa06a0
 #define CPUID_METEORLAKE_A0_2		0xa06a1
+#define CPUID_RAPTORLAKE_J0		0xb06a2
+
 #endif /* CPU_INTEL_CPU_IDS_H */
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 7c460f9..e1d55b7 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3075,6 +3075,8 @@
 #define PCI_DID_INTEL_ADP_M_N_ESPI_30			0x549e
 #define PCI_DID_INTEL_ADP_M_N_ESPI_31			0x549f
 #define PCI_DID_INTEL_ADP_M_ESPI_32			0x5186
+#define PCI_DID_INTEL_RPL_P_ESPI_0			0x519c
+#define PCI_DID_INTEL_RPL_P_ESPI_1			0x519d
 #define PCI_DID_INTEL_SPR_ESPI_1			0x1b80
 #define PCI_DID_INTEL_MTL_ESPI_0			0x7e00
 #define PCI_DID_INTEL_MTL_ESPI_1			0x7e01
@@ -3434,6 +3436,10 @@
 #define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11		0x7ecb
 #define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12		0x7ecc

+#define PCI_DID_INTEL_RPL_P_PCIE_RP1			0xa74d
+#define PCI_DID_INTEL_RPL_P_PCIE_RP2			0xa70d
+#define PCI_DID_INTEL_RPL_P_PCIE_RP3			0xa72d
+
 /* Intel SATA device Ids */
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE			0x8c00
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI			0x8c02
@@ -3959,6 +3965,8 @@
 #define PCI_DID_INTEL_MTL_M_GT2				0x7d40
 #define PCI_DID_INTEL_MTL_P_GT2_1			0x7d50
 #define PCI_DID_INTEL_MTL_P_GT2_2			0x7d60
+#define PCI_DID_INTEL_RPL_P_GT1				0xa720
+#define PCI_DID_INTEL_RPL_P_GT2				0xa7a8

/* Intel Northbridge Ids */
@@ -4079,6 +4087,7 @@
 #define PCI_DID_INTEL_MTL_M_ID			0x7D00
 #define PCI_DID_INTEL_MTL_P_ID_1		0x7D01
 #define PCI_DID_INTEL_MTL_P_ID_2		0x7D02
+#define PCI_DID_INTEL_RPL_P_ID_1		0xa706

/* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22
@@ -4137,6 +4146,7 @@
 #define PCI_DID_INTEL_MTL_XHCI			0x7e7d
 #define PCI_DID_INTEL_MTL_M_TCSS_XHCI		0x7eb0
 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI		0x7ec0
+#define PCI_DID_INTEL_RPL_TCSS_XHCI		0xa71e

/* Intel P2SB device Ids */
 #define PCI_DID_INTEL_APL_P2SB			0x5a92
@@ -4337,6 +4347,11 @@
 #define PCI_DID_INTEL_MTL_M_TBT_DMA0		0x7eb2
 #define PCI_DID_INTEL_MTL_P_TBT_DMA0		0x7ec2
 #define PCI_DID_INTEL_MTL_P_TBT_DMA1		0x7ec3
+#define PCI_DID_INTEL_RPL_TBT_RP0		0xa76e
+#define PCI_DID_INTEL_RPL_TBT_RP1		0xa73f
+#define PCI_DID_INTEL_RPL_TBT_RP2		0xa72f
+#define PCI_DID_INTEL_RPL_TBT_DMA0		0xa73e
+#define PCI_DID_INTEL_RPL_TBT_DMA1		0xa76d

/* Intel WIFI Ids */
 #define PCI_DID_1000_SERIES_WIFI		0x0084
@@ -4376,6 +4391,7 @@
 #define PCI_DID_INTEL_ADL_IPU			0x465d
 #define PCI_DID_INTEL_ADL_N_IPU			0x462e
 #define PCI_DID_INTEL_MTL_IPU			0x7d19
+#define PCI_DID_INTEL_RPL_IPU			0xa75d

/* Intel Dynamic Tuning Technology Device */
 #define PCI_DID_INTEL_CML_DTT			0x1903
@@ -4383,6 +4399,7 @@
 #define PCI_DID_INTEL_JSL_DTT			0x4E03
 #define PCI_DID_INTEL_ADL_DTT			0x461d
 #define PCI_DID_INTEL_MTL_DTT			0x7d03
+#define PCI_DID_INTEL_RPL_DTT			0xa71d

/* Intel CNVi WiFi/BT device IDs */
 #define PCI_DID_INTEL_CML_LP_CNVI_WIFI		0x02f0
@@ -4427,6 +4444,7 @@
 #define PCI_DID_INTEL_ADP_N_PMC_CRASHLOG_SRAM		0x54ef
 #define PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM		0xa0ef
 #define PCI_DID_INTEL_MTL_CRASHLOG_SRAM			0x7d0d
+#define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM		0xa77d

#define PCI_VID_COMPUTONE		0x8e0e
 #define PCI_DID_COMPUTONE_IP2EX		0x0291
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c
index bdce2b7..a650b23 100644
--- a/src/soc/intel/alderlake/bootblock/report_platform.c
+++ b/src/soc/intel/alderlake/bootblock/report_platform.c
@@ -29,6 +29,7 @@
    { CPUID_ALDERLAKE_Q0, "Alderlake Q0 Platform" },
    { CPUID_ALDERLAKE_R0, "Alderlake R0 Platform" },
    { CPUID_ALDERLAKE_N_A0, "Alderlake-N Platform" },
+	{ CPUID_RAPTORLAKE_J0, "Raptorlake Platform" },
 };

static struct {
@@ -50,6 +51,7 @@
    { PCI_DID_INTEL_ADL_N_ID_2, "Alderlake-N" },
    { PCI_DID_INTEL_ADL_N_ID_3, "Alderlake-N" },
    { PCI_DID_INTEL_ADL_N_ID_4, "Alderlake-N" },
+	{ PCI_DID_INTEL_RPL_P_ID_1, "Raptorlake-P" },

};

@@ -94,6 +96,8 @@
    { PCI_DID_INTEL_ADP_M_ESPI_32, "Alderlake-M SKU" },
    { PCI_DID_INTEL_ADP_M_N_ESPI_1, "Alderlake-N SKU" },
    { PCI_DID_INTEL_ADP_M_N_ESPI_2, "Alderlake-N SKU" },
+	{ PCI_DID_INTEL_RPL_P_ESPI_0, "Raptorlake-P SKU" },
+	{ PCI_DID_INTEL_RPL_P_ESPI_1, "Raptorlake-P SKU" },
 };

static struct {
@@ -127,6 +131,8 @@
    { PCI_DID_INTEL_ADL_N_GT1, "Alderlake N GT1" },
    { PCI_DID_INTEL_ADL_N_GT2, "Alderlake N GT2" },
    { PCI_DID_INTEL_ADL_N_GT3, "Alderlake N GT3" },
+	{ PCI_DID_INTEL_RPL_P_GT1, "Raptorlake P GT1" },
+	{ PCI_DID_INTEL_RPL_P_GT2, "Raptorlake P GT2" },
 };

static inline uint8_t get_dev_revision(pci_devfn_t dev)
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 7d4fb9c..48089f3 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -231,6 +231,10 @@
    	PCI_DID_INTEL_ADL_N_ID_4,
    };

+	const uint16_t rpl_p_mch_ids[] = {
+		PCI_DID_INTEL_RPL_P_ID_1,
+	};
+
    const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT),
    						   PCI_FUNC(SA_DEVFN_ROOT)),
    					   PCI_DEVICE_ID);
@@ -255,6 +259,11 @@
    		return ADL_N;
    }

+	for (size_t i = 0; i < ARRAY_SIZE(adl_p_mch_ids); i++) {
+		if (rpl_p_mch_ids[i] == mchid)
+			return RPL_P;
+	}
+
    return ADL_UNKNOWN;
 }

@@ -265,6 +274,7 @@
    case ADL_M: /* fallthrough */
    case ADL_N:
    case ADL_P:
+	case RPL_P:
    	return LPM_S0i2_0 | LPM_S0i3_0;
    case ADL_S:
    	return LPM_S0i2_0 | LPM_S0i2_1;
diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h
index cd6f34f..424e02a 100644
--- a/src/soc/intel/alderlake/include/soc/cpu.h
+++ b/src/soc/intel/alderlake/include/soc/cpu.h
@@ -25,6 +25,7 @@
    ADL_N,
    ADL_P,
    ADL_S,
+	RPL_P,
 };

enum adl_cpu_type get_adl_cpu_type(void);
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 823f23e..853851a 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -76,6 +76,7 @@
    { X86_VENDOR_INTEL, CPUID_ALDERLAKE_Q0 },
    { X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0 },
    { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0 },
+	{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_J0 },
    { 0, 0 },
 };

diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c
index 5fe883c..a1a03ec 100644
--- a/src/soc/intel/common/block/dtt/dtt.c
+++ b/src/soc/intel/common/block/dtt/dtt.c
@@ -5,6 +5,7 @@
 #include <device/pci_ids.h>

static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_RPL_DTT,
    PCI_DID_INTEL_MTL_DTT,
    PCI_DID_INTEL_CML_DTT,
    PCI_DID_INTEL_TGL_DTT,
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 5fc67aa..c142aff 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -177,6 +177,8 @@
 };

static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_RPL_P_GT1,
+	PCI_DID_INTEL_RPL_P_GT2,
    PCI_DID_INTEL_MTL_M_GT2,
    PCI_DID_INTEL_MTL_P_GT2_1,
    PCI_DID_INTEL_MTL_P_GT2_2,
diff --git a/src/soc/intel/common/block/ipu/ipu.c b/src/soc/intel/common/block/ipu/ipu.c
index ead4094..a496f0a 100644
--- a/src/soc/intel/common/block/ipu/ipu.c
+++ b/src/soc/intel/common/block/ipu/ipu.c
@@ -12,6 +12,7 @@
 };

static const uint16_t pci_device_ids[] = {
+	PCI_DID_INTEL_RPL_IPU,
    PCI_DID_INTEL_TGL_IPU,
    PCI_DID_INTEL_TGL_H_IPU,
    PCI_DID_INTEL_JSL_IPU,
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index 81c7a6e..89d9892 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -138,6 +138,8 @@
 };

static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_RPL_P_ESPI_0,
+	PCI_DID_INTEL_RPL_P_ESPI_1,
    PCI_DID_INTEL_MTL_ESPI_0,
    PCI_DID_INTEL_MTL_ESPI_1,
    PCI_DID_INTEL_MTL_ESPI_2,
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 11038ab..d435286 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -66,6 +66,9 @@
 };

static const unsigned short pcie_device_ids[] = {
+	PCI_DID_INTEL_RPL_P_PCIE_RP1,
+	PCI_DID_INTEL_RPL_P_PCIE_RP2,
+	PCI_DID_INTEL_RPL_P_PCIE_RP3,
    PCI_DID_INTEL_MTL_SOC_PCIE_RP1,
    PCI_DID_INTEL_MTL_SOC_PCIE_RP2,
    PCI_DID_INTEL_MTL_SOC_PCIE_RP3,
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 07bcb0c..a0b28fb 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -443,6 +443,7 @@
    PCI_DID_INTEL_ADL_N_ID_2,
    PCI_DID_INTEL_ADL_N_ID_3,
    PCI_DID_INTEL_ADL_N_ID_4,
+	PCI_DID_INTEL_RPL_P_ID_1,
    0
 };

diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c
index 86bd09b..d62496e 100644
--- a/src/soc/intel/common/block/usb4/usb4.c
+++ b/src/soc/intel/common/block/usb4/usb4.c
@@ -53,6 +53,8 @@
 #endif

static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_RPL_TBT_DMA0,
+	PCI_DID_INTEL_RPL_TBT_DMA1,
    PCI_DID_INTEL_MTL_M_TBT_DMA0,
    PCI_DID_INTEL_MTL_P_TBT_DMA0,
    PCI_DID_INTEL_MTL_P_TBT_DMA1,
diff --git a/src/soc/intel/common/block/usb4/xhci.c b/src/soc/intel/common/block/usb4/xhci.c
index 20ed2a5..bc2bc43 100644
--- a/src/soc/intel/common/block/usb4/xhci.c
+++ b/src/soc/intel/common/block/usb4/xhci.c
@@ -26,6 +26,7 @@
 };

static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_RPL_TCSS_XHCI,
    PCI_DID_INTEL_MTL_M_TCSS_XHCI,
    PCI_DID_INTEL_MTL_P_TCSS_XHCI,
    PCI_DID_INTEL_TGP_TCSS_XHCI,