Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 )

Change subject: soc/intel/tigerlake: Do initial SoC commit till ramstage
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Patch Set 16:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36087/16/src/soc/intel/tigerlake/in... 
File src/soc/intel/tigerlake/include/soc/ramstage.h:

https://review.coreboot.org/c/coreboot/+/36087/16/src/soc/intel/tigerlake/in... 
PS16, Line 24: void mainboard_silicon_init_params(FSP_S_CONFIG *params);
need consistent spacing around '*' (ctx:WxV)