Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
sb/intel/common: Properly guard USB debug
The declarations in usb_debug.c needs to be guarded in order to not conflict with other chipsets.
Change-Id: I84c3401b9419f2878c2cfdf81147fa854018f9ae Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/fsp_rangeley/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 10 files changed, 15 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/36878/1
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index f561fe5..c01e2b9 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -47,6 +47,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config EHCI_BAR hex diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 57c0dbe..55134a6 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -46,6 +46,9 @@ config SOUTHBRIDGE_INTEL_COMMON_FINALIZE bool
+config SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + bool + config INTEL_DESCRIPTOR_MODE_CAPABLE def_bool n help diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 9ff0ebc..c8521e1 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -28,9 +28,9 @@ all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c
-bootblock-$(CONFIG_USBDEBUG) += usb_debug.c -romstage-$(CONFIG_USBDEBUG) += usb_debug.c -ramstage-$(CONFIG_USBDEBUG) += usb_debug.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index 56c02b5..b69883f 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -34,6 +34,7 @@ select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config EHCI_BAR hex diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 916560a..3fdc674 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -23,6 +23,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 17ee4fc..6e7910f 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -33,6 +33,7 @@ select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
if SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index cd2f76d..bb80408 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -33,6 +33,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
if SOUTHBRIDGE_INTEL_I82801IX
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 7f44fcf..8db8e0c 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -35,7 +35,8 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE - select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
if SOUTHBRIDGE_INTEL_I82801JX
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index c84a66d..b419f34 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -45,6 +45,7 @@ select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config EHCI_BAR hex diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 95b9f62..ef071f2 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -45,6 +45,7 @@ select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config INTEL_LYNXPOINT_LP bool
Hello Patrick Rudolph, Mike Banon, Nico Huber, David Guckian, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36878
to look at the new patch set (#2).
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
sb/intel/common: Properly guard USB debug
The declarations in usb_debug.c needs to be guarded in order to not conflict with other chipsets.
Change-Id: I84c3401b9419f2878c2cfdf81147fa854018f9ae Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/fsp_rangeley/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 10 files changed, 14 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/36878/2
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
Patch Set 2: Code-Review+1
Thank you, it works, although an alternative solution is also possible - please check it at CB:36879
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/commo... File src/southbridge/intel/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/commo... PS2, Line 31: bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c please add ifeq ($(CONFIG_USBDEBUG),y) to reduce build time on all boards using SB_INTEL_COMMON
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/commo... File src/southbridge/intel/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/commo... PS2, Line 31: bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
please add ifeq ($(CONFIG_USBDEBUG),y) to reduce build time on all boards using SB_INTEL_COMMON
I wouldn't be surprised if more than half of the files here alone get GC depending on some other Kconfig symbol. We build things that get GC all over coreboot. The reason for not caring are: - Things get build tested regardless of Kconfig - The increase in build time is little since ccache is used.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
Patch Set 2: Code-Review+1
Missing fsp_broadwell_de, that had it before, cf. `git show --stat 1d4bdda`.
(ICH4 really has EHCI, I had to check, now I feel old for some reason)
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
Patch Set 2:
(1 comment)
Missing fsp_broadwell_de, that had it before, cf. `git show --stat 1d4bdda`.
But it doesn't HAVE_USBDEBUG? nvm.
I think we can move HAVE_USBDEBUG to `common/`, though. Only keep HAVE_USBDEBUG_OPTIONS local.
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/i8280... File src/southbridge/intel/i82801dx/Kconfig:
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/i8280... PS2, Line 22: select HAVE_USBDEBUG Move to common/ please.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
Patch Set 2:
Patch Set 2: Code-Review+1
Missing fsp_broadwell_de, that had it before, cf. `git show --stat 1d4bdda`.
(ICH4 really has EHCI, I had to check, now I feel old for some reason)
I figured it was bogus since it likely needs HAVE_USBDEBUG_OPTIONS to use 1d.0 instead of 1d.7 which is not present in devicetrees of boards using this target.
Hello Patrick Rudolph, Mike Banon, Patrick Rudolph, build bot (Jenkins), Nico Huber, David Guckian, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36878
to look at the new patch set (#3).
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
sb/intel/common: Properly guard USB debug
The declarations in usb_debug.c needs to be guarded in order to not conflict with other chipsets.
Change-Id: I84c3401b9419f2878c2cfdf81147fa854018f9ae Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/fsp_rangeley/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 10 files changed, 15 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/36878/3
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/i8280... File src/southbridge/intel/i82801dx/Kconfig:
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/i8280... PS2, Line 22: select HAVE_USBDEBUG
Move to common/ please.
Done
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
Patch Set 3: Code-Review+2
Thank you very much!
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
Patch Set 3:
I wonder if we should start calling it EHCI debug to make distinction. I think I saw some preliminary xHCI code landing.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/commo... File src/southbridge/intel/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/commo... PS2, Line 31: bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
please add ifeq ($(CONFIG_USBDEBUG),y) to reduce build time on all boards using SB_INTEL_COMMON […]
Should that be done for all user selectable options?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
Patch Set 3:
(1 comment)
Patch Set 3:
I wonder if we should start calling it EHCI debug to make distinction. I think I saw some preliminary xHCI code landing.
Interesting.
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/commo... File src/southbridge/intel/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/commo... PS2, Line 31: bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
Should that be done for all user selectable options?
If no behaviour is changed build testing code is worth the often small increase in buildtime IMO.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/commo... File src/southbridge/intel/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/commo... PS2, Line 31: bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
please add ifeq ($(CONFIG_USBDEBUG),y) to reduce build time on all boards using SB_INTEL_COMMON […]
There are at least two things to consider before removing guards: * Overrides of `weak` symbols. * Code we don't gc, e.g. dynamically hooked-up drivers, BS hooks.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/commo... File src/southbridge/intel/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/commo... PS2, Line 31: bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
There are at least two things to consider before removing guards:
- Overrides of `weak` symbols.
- Code we don't gc, e.g. dynamically hooked-up drivers, BS hooks.
Basically, if BUILD_TIMELESS=1 is the same it's ok ;)
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/commo... File src/southbridge/intel/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/36878/2/src/southbridge/intel/commo... PS2, Line 31: bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
There are at least two things to consider before removing guards: […]
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36878 )
Change subject: sb/intel/common: Properly guard USB debug ......................................................................
sb/intel/common: Properly guard USB debug
The declarations in usb_debug.c needs to be guarded in order to not conflict with other chipsets.
Change-Id: I84c3401b9419f2878c2cfdf81147fa854018f9ae Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/36878 Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Mike Banon mikebdp2@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/fsp_rangeley/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 10 files changed, 15 insertions(+), 9 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Mike Banon: Looks good to me, approved
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index f561fe5..c01e2b9 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -47,6 +47,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config EHCI_BAR hex diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 57c0dbe..18bcd2e 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -46,6 +46,10 @@ config SOUTHBRIDGE_INTEL_COMMON_FINALIZE bool
+config SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + def_bool n + select HAVE_USBDEBUG + config INTEL_DESCRIPTOR_MODE_CAPABLE def_bool n help diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 9ff0ebc..c8521e1 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -28,9 +28,9 @@ all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c
-bootblock-$(CONFIG_USBDEBUG) += usb_debug.c -romstage-$(CONFIG_USBDEBUG) += usb_debug.c -ramstage-$(CONFIG_USBDEBUG) += usb_debug.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index 56c02b5..076a2bc 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -23,7 +23,6 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC - select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK @@ -34,6 +33,7 @@ select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config EHCI_BAR hex diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 916560a..5dad02e 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -19,10 +19,10 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC select HAVE_SMI_HANDLER - select HAVE_USBDEBUG select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index bf9880a..2d95fc2 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -17,7 +17,6 @@ bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC - select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select COMMON_FADT @@ -33,6 +32,7 @@ select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
if SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index cd2f76d..8363978 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -23,7 +23,6 @@ select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET select IOAPIC - select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS @@ -33,6 +32,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
if SOUTHBRIDGE_INTEL_I82801IX
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 7f44fcf..161290f 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -24,7 +24,6 @@ select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET select IOAPIC - select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS @@ -36,6 +35,7 @@ select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
if SOUTHBRIDGE_INTEL_I82801JX
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index c84a66d..f9723fb 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -22,7 +22,6 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC - select HAVE_USBDEBUG select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM @@ -45,6 +44,7 @@ select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config EHCI_BAR hex diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 95b9f62..ef071f2 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -45,6 +45,7 @@ select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config INTEL_LYNXPOINT_LP bool
-
Arthur Heymans (Code Review) -
Kyösti Mälkki (Code Review)
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Mike Banon (Code Review)
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Nico Huber (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)