Change in ...coreboot[master]: src/mainboard/protectli/vault_kbl: Add FW6 boards support
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33839
Change subject: src/mainboard/protectli/vault_kbl: Add FW6 boards support ......................................................................
src/mainboard/protectli/vault_kbl: Add FW6 boards support
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 --- A src/mainboard/protectli/Kconfig A src/mainboard/protectli/Kconfig.name A src/mainboard/protectli/vault_kbl/Kconfig A src/mainboard/protectli/vault_kbl/Kconfig.name A src/mainboard/protectli/vault_kbl/Makefile.inc A src/mainboard/protectli/vault_kbl/acpi/ec.asl A src/mainboard/protectli/vault_kbl/acpi/mainboard.asl A src/mainboard/protectli/vault_kbl/acpi/superio.asl A src/mainboard/protectli/vault_kbl/acpi_tables.c A src/mainboard/protectli/vault_kbl/board_info.txt A src/mainboard/protectli/vault_kbl/bootblock.c A src/mainboard/protectli/vault_kbl/devicetree.cb A src/mainboard/protectli/vault_kbl/dsdt.asl A src/mainboard/protectli/vault_kbl/gpio.h A src/mainboard/protectli/vault_kbl/hda_verb.c A src/mainboard/protectli/vault_kbl/mainboard.c A src/mainboard/protectli/vault_kbl/ramstage.c A src/mainboard/protectli/vault_kbl/romstage.c A src/mainboard/protectli/vault_kbl/smihandler.c 19 files changed, 993 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33839/1
diff --git a/src/mainboard/protectli/Kconfig b/src/mainboard/protectli/Kconfig new file mode 100644 index 0000000..2e63af6 --- /dev/null +++ b/src/mainboard/protectli/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_PROTECTLI + +choice + prompt "Mainboard model" + +source "src/mainboard/protectli/*/Kconfig.name" + +endchoice + +source "src/mainboard/protectli/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Protectli" + +endif # VENDOR_PROTECTLI diff --git a/src/mainboard/protectli/Kconfig.name b/src/mainboard/protectli/Kconfig.name new file mode 100644 index 0000000..adc7f05 --- /dev/null +++ b/src/mainboard/protectli/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_PROTECTLI + bool "Protectli" diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig new file mode 100644 index 0000000..06b6d7a --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/Kconfig @@ -0,0 +1,56 @@ +if BOARD_PROTECTLI_FW6 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_KABYLAKE + select MAINBOARD_USES_FSP2_0 + select SUPERIO_ITE_IT8772F + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "protectli/vault_kbl" + +config MAINBOARD_PART_NUMBER + string + default "FW6" + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xd00 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config USE_INTEL_FSP_MP_INIT + bool + default n + +config USE_COREBOOT_NATIVE_MP_INIT + bool + default y + +config MAX_CPUS + int + default 4 + +config VGA_BIOS_ID + string + default "8086,5916" # 8086,5906 for FW6A + +config CBFS_SIZE + hex + default 0x600000 + +endif diff --git a/src/mainboard/protectli/vault_kbl/Kconfig.name b/src/mainboard/protectli/vault_kbl/Kconfig.name new file mode 100644 index 0000000..1b1606b --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_PROTECTLI_FW6 + bool "Vault FW6" + diff --git a/src/mainboard/protectli/vault_kbl/Makefile.inc b/src/mainboard/protectli/vault_kbl/Makefile.inc new file mode 100644 index 0000000..81d3ce2 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c + +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/protectli/vault_kbl/acpi/ec.asl b/src/mainboard/protectli/vault_kbl/acpi/ec.asl new file mode 100644 index 0000000..8b47d94 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/acpi/ec.asl @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + diff --git a/src/mainboard/protectli/vault_kbl/acpi/mainboard.asl b/src/mainboard/protectli/vault_kbl/acpi/mainboard.asl new file mode 100644 index 0000000..62e73dc --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/acpi/mainboard.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } +} diff --git a/src/mainboard/protectli/vault_kbl/acpi/superio.asl b/src/mainboard/protectli/vault_kbl/acpi/superio.asl new file mode 100644 index 0000000..de9dc8c --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/acpi/superio.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/protectli/vault_kbl/acpi_tables.c b/src/mainboard/protectli/vault_kbl/acpi_tables.c new file mode 100644 index 0000000..cb243b3 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/acpi_tables.c @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ \ No newline at end of file diff --git a/src/mainboard/protectli/vault_kbl/board_info.txt b/src/mainboard/protectli/vault_kbl/board_info.txt new file mode 100644 index 0000000..a3fb505 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Kabylake RVP Reference Board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/protectli/vault_kbl/bootblock.c b/src/mainboard/protectli/vault_kbl/bootblock.c new file mode 100644 index 0000000..f8f32de --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/bootblock.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <bootblock_common.h> +#include <superio/ite/it8772f/it8772f.h> +#include <superio/ite/common/ite.h> + +#define CLKIN_DEV PNP_DEV(0x2e, IT8772F_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8772F_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_3vsbsw(CLKIN_DEV); + ite_kill_watchdog(CLKIN_DEV); + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb new file mode 100644 index 0000000..acdb6e0 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -0,0 +1,314 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + register "s0ix_enable" = "1" + + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c03e1" + register "gen4_dec" = "0x001c02e1" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + register "eist_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # Enable VT-d + register "ignore_vtd" = "0" + + # Enable SERIRQ continuous + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "tcc_offset" = "5" # TCC of 95C + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPwrOptEnable" = "1" + register "EnableAzalia" = "0" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "0" + register "HeciEnabled" = "1" + register "PmTimerDisabled" = "1" + register "SaGv" = "SaGv_Enabled" + register "SaImguEnable" = "0" + register "IslVrCmd" = "2" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "4" # 4s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 240, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable SATA ports 1,2 + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "0" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + + # Enable Root ports. 1-6 for LAN and Root Port 9 + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[8]" = "1" # mPCIe WiFi + + # Enable Advanced Error Reporting for RP 1-6, 9 + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpAdvancedErrorReporting[1]" = "1" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + + # Enable Latency Tolerance Reporting Mechanism RP 1-6, 9 + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[1]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + # Enable RP 9 CLKREQ# support + register "PcieRpClkReqSupport[8]" = "1" + # RP 9 uses CLKREQ0# + register "PcieRpClkReqNumber[8]" = "0" + + # Clocks 0-5 for RP 1-6 + register "PcieRpClkSrcNumber[0]" = "0" + register "PcieRpClkSrcNumber[1]" = "1" + register "PcieRpClkSrcNumber[2]" = "2" + register "PcieRpClkSrcNumber[3]" = "3" + register "PcieRpClkSrcNumber[4]" = "4" + register "PcieRpClkSrcNumber[5]" = "5" + # RP 9 shares CLKSRC5# with RP 6 + register "PcieRpClkSrcNumber[8]" = "5" + + + # USB 2.0 enable ports 1-8, disable ports 9-12 + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disabled + + # USB 3.0 enable ports 1-4, disable ports 5-6 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled + + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Lock Down CHIPSET_LOCKDOWN_FSP + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # Thermal Subsystem + device pci 14.3 off end # Camera I/O Host Controller + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 on end # PCI Express Port 2 + device pci 1c.2 on end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + chip superio/ite/it8772f + register "peci_tmpin" = "3" + register "tmpin1_mode" = "THERMAL_RESISTOR" + register "tmpin2_mode" = "THERMAL_RESISTOR" + # Enable FAN2 available on fan header + register "fan2_enable" = "1" + register "fan2_speed" = "0x60" + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa40 + io 0x62 = 0xa30 + irq 0x70 = 9 + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # IR + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/protectli/vault_kbl/dsdt.asl b/src/mainboard/protectli/vault_kbl/dsdt.asl new file mode 100644 index 0000000..ac929a6 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/dsdt.asl @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/protectli/vault_kbl/gpio.h b/src/mainboard/protectli/vault_kbl/gpio.h new file mode 100644 index 0000000..552397e --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/gpio.h @@ -0,0 +1,193 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIOFW6B_H +#define _GPIOFW6B_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PIRQA_N*/ PAD_CFG_TERM_GPO(GPP_A7, 1, NONE, DEEP), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), +/* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), +/* PME# */ PAD_CFG_NF(GPP_A11, 20K_PU, DEEP, NF1), +/* ISH_GP6 */ PAD_NC(GPP_A12, NONE), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PCH_SUSSTAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE ), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT_N */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0_N */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ1_N*/ PAD_NC(GPP_B6, NONE), +/* SRCCLKREQ2_N*/ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3_N*/ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4_N*/ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5_N*/ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE_N */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1), +/* GSPI0_CS_N */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS_N */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), +/* SML0_CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_CTS_N */ PAD_NC(GPP_C10, NONE), +/* UART0_RTS_N */ PAD_NC(GPP_C11, NONE), +/* UART1_RXD */ PAD_NC(GPP_C12, NONE), +/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_CTS_N */ PAD_NC(GPP_C14, NONE), +/* UART1_RTS_N */ PAD_NC(GPP_C15, NONE), +/* I2C0_SDA */ PAD_NC(GPP_C16, NONE), +/* I2C0_SCL */ PAD_NC(GPP_C17, NONE), +/* I2C1_SDA */ PAD_NC(GPP_C18, NONE), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), +/* UART2_RXD */ PAD_NC(GPP_C20, NONE), +/* UART2_TXD */ PAD_NC(GPP_C21, NONE), +/* UART2_CTS_N */ PAD_NC(GPP_C22, NONE), +/* UART2_RTS_N */ PAD_NC(GPP_C23, NONE), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* FLASHTRIG */ PAD_NC(GPP_D4, NONE), +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* GPP_D9 */ PAD_NC(GPP_D9, NONE), +/* GPP_D10 */ PAD_NC(GPP_D10, NONE), +/* GPP_D11 */ PAD_NC(GPP_D11, NONE), +/* GPP_D12 */ PAD_NC(GPP_D12, NONE), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK_1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA_1 */ PAD_NC(GPP_D18, NONE), +/* DMIC_CLK_0 */ PAD_NC(GPP_D19, NONE), +/* DMIC_DATA_0 */ PAD_NC(GPP_D20, NONE), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), +/* I2S_MCLK */ PAD_NC(GPP_D23, NONE), +/* SATAXPCIE0 (TP8) */ PAD_NC(GPP_E0, NONE), +/* SATAXPCIE1 (TP9)*/ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 (TP10) */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_NC(GPP_E7, NONE), +/* SATA_LED */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_NC(GPP_E9, NONE), +/* USB2_OC_1 */ PAD_NC(GPP_E10, NONE), +/* USB2_OC_2 */ PAD_NC(GPP_E11, NONE), +/* USB2_OC_3 */ PAD_NC(GPP_E12, NONE), +/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDI2_HPD */ PAD_NC(GPP_E14, NONE), +/* DDI3_HPD */ PAD_NC(GPP_E15, NONE), +/* DDI4_HPD */ PAD_NC(GPP_E16, NONE), +/* EDP_HPD */ PAD_NC(GPP_E17, NONE), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F9, NONE), +/* I2C5_SDA */ PAD_NC(GPP_F10, NONE), +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* GPP_F23 */ PAD_NC(GPP_F23, NONE), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), +/* PCH_BATLOW */ PAD_NC(GPD0, NONE), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* LAN_WAKE_N */ PAD_NC(GPD2, NONE), +/* PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# (TP7) */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* GPD7_RSVD */ PAD_CFG_TERM_GPO(GPD7, 1, NONE, DEEP), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* SLP_WLAN# (TP6) */ PAD_NC(GPD9, NONE), +/* SLP_S5# (TP3) */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_NC(GPD11, NONE), +}; + +#endif + +#endif diff --git a/src/mainboard/protectli/vault_kbl/hda_verb.c b/src/mainboard/protectli/vault_kbl/hda_verb.c new file mode 100644 index 0000000..ea3c37f --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/hda_verb.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki naresh.solanki@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; \ No newline at end of file diff --git a/src/mainboard/protectli/vault_kbl/mainboard.c b/src/mainboard/protectli/vault_kbl/mainboard.c new file mode 100644 index 0000000..58d0768 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/mainboard.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <stdlib.h> + +static void mainboard_final(void *unused) +{ +} + +struct chip_operations mainboard_ops = { + .final = mainboard_final, +}; diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/ramstage.c new file mode 100644 index 0000000..07b98a4 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/ramstage.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016-2018 Intel Corporation + * Copyright 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <soc/ramstage.h> + +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->TurboMode = 1; + params->PchThermalDeviceEnable = 0; + params->PchPort61hEnable = 1; + params->CdClock = 3; + params->GmmEnable = 0; +} + diff --git a/src/mainboard/protectli/vault_kbl/romstage.c b/src/mainboard/protectli/vault_kbl/romstage.c new file mode 100644 index 0000000..c53112a --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/romstage.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016-2018 Intel Corporation. + * Copyright 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <soc/gpio.h> +#include <spd_bin.h> + +#include "gpio.h" + +static void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 2, 3, 4, 5, 6, 7 }, + { 1, 0, 2, 3, 4, 5, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[5] = { + 100, 40, 20, 20, 26 }; + + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + + struct spd_block blk = { + .addr_map = { 0x50, 0x52, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; + get_spd_smbus(&blk); + dump_spd_info(&blk); + + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} diff --git a/src/mainboard/protectli/vault_kbl/smihandler.c b/src/mainboard/protectli/vault_kbl/smihandler.c new file mode 100644 index 0000000..d2df31d --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/smihandler.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <soc/iomap.h> +#include <soc/nvs.h> +#include <soc/pm.h> +#include <soc/smm.h> + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + return 1; +} + +void mainboard_smi_gpi_handler(const struct gpi_status *sts) +{ +} + +void mainboard_smi_sleep(u8 slp_typ) +{ +} + +int mainboard_smi_apmc(u8 apmc) +{ + return 0; +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: src/mainboard/protectli/vault_kbl: Add FW6 boards support ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/#/c/33839/1/src/mainboard/protectli/vault_kbl/ac... File src/mainboard/protectli/vault_kbl/acpi_tables.c:
https://review.coreboot.org/#/c/33839/1/src/mainboard/protectli/vault_kbl/ac... PS1, Line 15: */ adding a line without newline at end of file
https://review.coreboot.org/#/c/33839/1/src/mainboard/protectli/vault_kbl/gp... File src/mainboard/protectli/vault_kbl/gpio.h:
https://review.coreboot.org/#/c/33839/1/src/mainboard/protectli/vault_kbl/gp... PS1, Line 50: /* ISH_GP5 */ PAD_NC(GPP_A23, NONE ), space prohibited before that close parenthesis ')'
https://review.coreboot.org/#/c/33839/1/src/mainboard/protectli/vault_kbl/gp... PS1, Line 52: /* CORE_VID1 */ PAD_NC(GPP_B1, NONE), trailing whitespace
https://review.coreboot.org/#/c/33839/1/src/mainboard/protectli/vault_kbl/hd... File src/mainboard/protectli/vault_kbl/hda_verb.c:
https://review.coreboot.org/#/c/33839/1/src/mainboard/protectli/vault_kbl/hd... PS1, Line 26: AZALIA_ARRAY_SIZES; adding a line without newline at end of file
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: src/mainboard/protectli/vault_kbl: Add FW6 boards support ......................................................................
Patch Set 1:
Will add documentation soon.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33839
to look at the new patch set (#2).
Change subject: src/mainboard/protectli/vault_kbl: Add FW6 boards support ......................................................................
src/mainboard/protectli/vault_kbl: Add FW6 boards support
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 --- A src/mainboard/protectli/Kconfig A src/mainboard/protectli/Kconfig.name A src/mainboard/protectli/vault_kbl/Kconfig A src/mainboard/protectli/vault_kbl/Kconfig.name A src/mainboard/protectli/vault_kbl/Makefile.inc A src/mainboard/protectli/vault_kbl/acpi/ec.asl A src/mainboard/protectli/vault_kbl/acpi/mainboard.asl A src/mainboard/protectli/vault_kbl/acpi/superio.asl A src/mainboard/protectli/vault_kbl/acpi_tables.c A src/mainboard/protectli/vault_kbl/board_info.txt A src/mainboard/protectli/vault_kbl/bootblock.c A src/mainboard/protectli/vault_kbl/devicetree.cb A src/mainboard/protectli/vault_kbl/dsdt.asl A src/mainboard/protectli/vault_kbl/gpio.h A src/mainboard/protectli/vault_kbl/hda_verb.c A src/mainboard/protectli/vault_kbl/mainboard.c A src/mainboard/protectli/vault_kbl/ramstage.c A src/mainboard/protectli/vault_kbl/romstage.c A src/mainboard/protectli/vault_kbl/smihandler.c 19 files changed, 993 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33839/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: src/mainboard/protectli/vault_kbl: Add FW6 boards support ......................................................................
Patch Set 2:
(5 comments)
You might want to try "make gitconfig", so that it catches lint errors before committing.
I guess this is WIP?
https://review.coreboot.org/#/c/33839/2/src/mainboard/protectli/vault_kbl/Kc... File src/mainboard/protectli/vault_kbl/Kconfig.name:
https://review.coreboot.org/#/c/33839/2/src/mainboard/protectli/vault_kbl/Kc... PS2, Line 4: Extra newline
https://review.coreboot.org/#/c/33839/2/src/mainboard/protectli/vault_kbl/ac... File src/mainboard/protectli/vault_kbl/acpi/ec.asl:
https://review.coreboot.org/#/c/33839/2/src/mainboard/protectli/vault_kbl/ac... PS2, Line 16: Extra newline
https://review.coreboot.org/#/c/33839/2/src/mainboard/protectli/vault_kbl/ac... File src/mainboard/protectli/vault_kbl/acpi_tables.c:
PS2: Copyright on what? If this file is not going to be used, please remove it, or leave it empty.
https://review.coreboot.org/#/c/33839/2/src/mainboard/protectli/vault_kbl/bo... File src/mainboard/protectli/vault_kbl/board_info.txt:
https://review.coreboot.org/#/c/33839/2/src/mainboard/protectli/vault_kbl/bo... PS2, Line 1: Vendor name: Intel : Board name: Kabylake RVP Reference Board I don't think so :D
https://review.coreboot.org/#/c/33839/2/src/mainboard/protectli/vault_kbl/ra... File src/mainboard/protectli/vault_kbl/ramstage.c:
https://review.coreboot.org/#/c/33839/2/src/mainboard/protectli/vault_kbl/ra... PS2, Line 35: Extra newline
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: src/mainboard/protectli/vault_kbl: Add FW6 boards support ......................................................................
Patch Set 2:
(1 comment)
It only lacks documentation. Board is bootable. Setting WIP anyway
https://review.coreboot.org/#/c/33839/2/src/mainboard/protectli/vault_kbl/bo... File src/mainboard/protectli/vault_kbl/board_info.txt:
https://review.coreboot.org/#/c/33839/2/src/mainboard/protectli/vault_kbl/bo... PS2, Line 1: Vendor name: Intel : Board name: Kabylake RVP Reference Board
I don't think so :D
oops
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 boards support ......................................................................
Patch Set 7:
(32 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/33839/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33839/4//COMMIT_MSG@7 PS4, Line 7: src/mainboard
mb
Done
https://review.coreboot.org/c/coreboot/+/33839/4//COMMIT_MSG@7 PS4, Line 7: boards
There are three boards... […]
Added an entry in Documentation which explains what are the board variants etc.
https://review.coreboot.org/c/coreboot/+/33839/4//COMMIT_MSG@8 PS4, Line 8:
Tested how?
What is tested and not tested was mentioned in Documentation
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/Kconfig:
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 22: FW6
Is the mainboard name "FW6" or "FW6x"? (x is either A, B or C)
Board is FW6 and I do not want to change this Kconfig option, because it is propagated to SMBIOS. Vendor BIOS had FW6 as part number for all variants. I know from my own experience that careless modification of SMBIOS causes a huge mess in a long time.
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 36: config USE_INTEL_FSP_MP_INIT : bool : default n : : config USE_COREBOOT_NATIVE_MP_INIT : bool : default y
Aren't these the default values already?
Indeed. Removed
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 50: default "8086,5916" # 8086,5906 for FW6A
Use variants?
Not necessary. Actually I would like to avoid it because of SMBIOS as mentioned in other comment. Resolved/workarounded VGA BIOS ID with libgfxinit
https://review.coreboot.org/c/coreboot/+/33839/2/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/33839/2/src/mainboard/protectli/vau... PS2, Line 4:
Extra newline
Done
https://review.coreboot.org/c/coreboot/+/33839/2/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/33839/2/src/mainboard/protectli/vau... PS2, Line 16:
Extra newline
Done
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 4: * Copyright (C) 2015 Google Inc.
Remove.
Done
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 5: * Copyright (C) 2016 Intel Corporation.
IANAL, but I don't believe changing copyright notices of others is a good idea.
Removed the Copyrights as coreboot uses AUTHORS file now
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 17: Scope (_SB)
Note that this file is already included inside the _SB scope in dsdt. […]
Done
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/acpi/superio.asl:
PS4:
Do empty files need copyright headers?
IIRC Jenkins complains on files without a proper header.
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 4: * Copyright (C) 2015 Google Inc.
Remove.
Done
https://review.coreboot.org/c/coreboot/+/33839/2/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/acpi_tables.c:
PS2:
Copyright on what? If this file is not going to be used, please remove it, or leave it empty.
IIRC Jenkins complains on files without the header
https://review.coreboot.org/c/coreboot/+/33839/2/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/board_info.txt:
https://review.coreboot.org/c/coreboot/+/33839/2/src/mainboard/protectli/vau... PS2, Line 1: Vendor name: Intel : Board name: Kabylake RVP Reference Board
oops
Ack
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/board_info.txt:
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 2: Board name: FW6A FW6B FW6C
How about "FW6 series" or "FW6x series" ?
Done
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 235: CHIPSET_LOCKDOWN_FSP
Really?
Corrected
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 20: "dsdt.aml",
Do we use tabs in coreboot to indent ASL files?
AFAIK yes.
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 28: // Some generic macros
Please drop. […]
Done
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 34: // CPU
This comment does not add much value, so I would also drop it
Done
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 37: Scope (_SB) { : Device (PCI0)
Device (_SB. […]
Done
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 45: // Chipset specific sleep states
This comment was also dropped
Done
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/gpio.h:
PS4:
If possible, consider using a gpio. […]
Not currently possible on skylake SoC IIRC. it would result in C file inclusion.
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/mainboard.c:
PS4:
Do you even need this file?
coreboot won't build without it
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 6: * Copyright (C) 2016 Intel Corporation.
Why?
Ack
https://review.coreboot.org/c/coreboot/+/33839/2/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/ramstage.c:
https://review.coreboot.org/c/coreboot/+/33839/2/src/mainboard/protectli/vau... PS2, Line 35:
Extra newline
Done
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/ramstage.c:
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 25: *
Ack
Done
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 26: gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
Isn't it indented with tabs already?
Done
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/romstage.c:
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 50: sizeof(RcompResistor));
One line.
Done
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 57: 100, 40, 20, 20, 26 };
This fits on a single line as well.
Done
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/smihandler.c:
PS4:
Does this board actually need a SMI handler?
Actually it doesn't. Removed file.
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 35: /* On success, the IO Trap Handler returns 0
Please use the comment style below: […]
File removed.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 boards support ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33839/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33839/6//COMMIT_MSG@7 PS6, Line 7: boards
board
There are 3 board variants, that is why I used plural
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33839
to look at the new patch set (#8).
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
mb/protectli/vault_kbl: Add FW6 support
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 --- M Documentation/mainboard/index.md A Documentation/mainboard/protectli/fw6.jpg A Documentation/mainboard/protectli/fw6.md M MAINTAINERS A src/mainboard/protectli/Kconfig A src/mainboard/protectli/Kconfig.name A src/mainboard/protectli/vault_kbl/Kconfig A src/mainboard/protectli/vault_kbl/Kconfig.name A src/mainboard/protectli/vault_kbl/Makefile.inc A src/mainboard/protectli/vault_kbl/acpi/ec.asl A src/mainboard/protectli/vault_kbl/acpi/mainboard.asl A src/mainboard/protectli/vault_kbl/acpi/superio.asl A src/mainboard/protectli/vault_kbl/acpi_tables.c A src/mainboard/protectli/vault_kbl/board_info.txt A src/mainboard/protectli/vault_kbl/bootblock.c A src/mainboard/protectli/vault_kbl/data.vbt A src/mainboard/protectli/vault_kbl/devicetree.cb A src/mainboard/protectli/vault_kbl/dsdt.asl A src/mainboard/protectli/vault_kbl/gma-mainboard.ads A src/mainboard/protectli/vault_kbl/gpio.h A src/mainboard/protectli/vault_kbl/hda_verb.c A src/mainboard/protectli/vault_kbl/mainboard.c A src/mainboard/protectli/vault_kbl/ramstage.c A src/mainboard/protectli/vault_kbl/romstage.c 24 files changed, 1,072 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33839/8
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 8:
(6 comments)
https://review.coreboot.org/c/coreboot/+/33839/8/Documentation/mainboard/pro... File Documentation/mainboard/protectli/fw6.jpg:
PS8: Would it be possible to have a picture of the internals instead?
https://review.coreboot.org/c/coreboot/+/33839/8/Documentation/mainboard/pro... File Documentation/mainboard/protectli/fw6.md:
https://review.coreboot.org/c/coreboot/+/33839/8/Documentation/mainboard/pro... PS8, Line 28: microcode Capitalize?
https://review.coreboot.org/c/coreboot/+/33839/8/Documentation/mainboard/pro... PS8, Line 31: graphics in BIOS We're not a steenkin' BIOS! How about: `pre-OS graphics` ?
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/Kconfig:
https://review.coreboot.org/c/coreboot/+/33839/4/src/mainboard/protectli/vau... PS4, Line 22: FW6
Board is FW6 and I do not want to change this Kconfig option, because it is propagated to SMBIOS. […]
Ack
https://review.coreboot.org/c/coreboot/+/33839/8/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/Kconfig:
https://review.coreboot.org/c/coreboot/+/33839/8/src/mainboard/protectli/vau... PS8, Line 46: config INTEL_GMA_VBT_FILE Isn't that the default path?
https://review.coreboot.org/c/coreboot/+/33839/8/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/acpi_tables.c:
PS8: This can go away
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 8: Code-Review+1
(2 comments)
I see there aren't any thermal zones set up for IT8772 fan control, how are you handling that?
https://review.coreboot.org/c/coreboot/+/33839/8/Documentation/mainboard/pro... File Documentation/mainboard/protectli/fw6.md:
https://review.coreboot.org/c/coreboot/+/33839/8/Documentation/mainboard/pro... PS8, Line 38: The first supported missing rest of sentence
https://review.coreboot.org/c/coreboot/+/33839/8/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/Kconfig:
https://review.coreboot.org/c/coreboot/+/33839/8/src/mainboard/protectli/vau... PS8, Line 5: select BOARD_ROMSIZE_KB_8192 : select HAVE_ACPI_RESUME : select HAVE_ACPI_TABLES : select SOC_INTEL_KABYLAKE : select SUPERIO_ITE_IT8772F : select MAINBOARD_HAS_LIBGFXINIT : select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS : select SPI_FLASH_MACRONIX alphabetize?
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/33839/8/Documentation/mainboard/pro... File Documentation/mainboard/protectli/fw6.jpg:
PS8:
Would it be possible to have a picture of the internals instead?
Yes, I guess
https://review.coreboot.org/c/coreboot/+/33839/8/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/Kconfig:
https://review.coreboot.org/c/coreboot/+/33839/8/src/mainboard/protectli/vau... PS8, Line 46: config INTEL_GMA_VBT_FILE
Isn't that the default path?
Unfortunately not.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 8:
Patch Set 8: Code-Review+1
(2 comments)
I see there aren't any thermal zones set up for IT8772 fan control, how are you handling that?
There is a fan connector on the mainboard, but it is not used on FW6. Left the fan enabled in case somebody would want to use it. it is configured for fixed speed, replicating vendor BIOS configuration.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33839/8/Documentation/mainboard/pro... File Documentation/mainboard/protectli/fw6.md:
https://review.coreboot.org/c/coreboot/+/33839/8/Documentation/mainboard/pro... PS8, Line 31: graphics in BIOS
We're not a steenkin' BIOS! How about: `pre-OS graphics` ?
It should be SeaBIOS or a pre-OS. Was writing it with having in mind a common person reading it (most of the people consider firmware=BIOS=UEFI). I agree, this is not nice.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Matt DeVillier, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33839
to look at the new patch set (#9).
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
mb/protectli/vault_kbl: Add FW6 support
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 --- M Documentation/mainboard/index.md A Documentation/mainboard/protectli/fw6.jpg A Documentation/mainboard/protectli/fw6.md M MAINTAINERS A src/mainboard/protectli/Kconfig A src/mainboard/protectli/Kconfig.name A src/mainboard/protectli/vault_kbl/Kconfig A src/mainboard/protectli/vault_kbl/Kconfig.name A src/mainboard/protectli/vault_kbl/Makefile.inc A src/mainboard/protectli/vault_kbl/acpi/ec.asl A src/mainboard/protectli/vault_kbl/acpi/mainboard.asl A src/mainboard/protectli/vault_kbl/acpi/superio.asl A src/mainboard/protectli/vault_kbl/board_info.txt A src/mainboard/protectli/vault_kbl/bootblock.c A src/mainboard/protectli/vault_kbl/data.vbt A src/mainboard/protectli/vault_kbl/devicetree.cb A src/mainboard/protectli/vault_kbl/dsdt.asl A src/mainboard/protectli/vault_kbl/gma-mainboard.ads A src/mainboard/protectli/vault_kbl/gpio.h A src/mainboard/protectli/vault_kbl/ramstage.c A src/mainboard/protectli/vault_kbl/romstage.c 21 files changed, 929 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33839/9
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33839/9/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/33839/9/src/mainboard/protectli/vau... PS9, Line 265: device pci 1c.1 on end # PCI Express Port 2 trailing whitespace
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Matt DeVillier, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33839
to look at the new patch set (#10).
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
mb/protectli/vault_kbl: Add FW6 support
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 --- M Documentation/mainboard/index.md A Documentation/mainboard/protectli/fw6.jpg A Documentation/mainboard/protectli/fw6.md M MAINTAINERS A src/mainboard/protectli/Kconfig A src/mainboard/protectli/Kconfig.name A src/mainboard/protectli/vault_kbl/Kconfig A src/mainboard/protectli/vault_kbl/Kconfig.name A src/mainboard/protectli/vault_kbl/Makefile.inc A src/mainboard/protectli/vault_kbl/acpi/ec.asl A src/mainboard/protectli/vault_kbl/acpi/mainboard.asl A src/mainboard/protectli/vault_kbl/acpi/superio.asl A src/mainboard/protectli/vault_kbl/board_info.txt A src/mainboard/protectli/vault_kbl/bootblock.c A src/mainboard/protectli/vault_kbl/data.vbt A src/mainboard/protectli/vault_kbl/devicetree.cb A src/mainboard/protectli/vault_kbl/dsdt.asl A src/mainboard/protectli/vault_kbl/gma-mainboard.ads A src/mainboard/protectli/vault_kbl/gpio.h A src/mainboard/protectli/vault_kbl/ramstage.c A src/mainboard/protectli/vault_kbl/romstage.c 21 files changed, 929 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33839/10
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 10:
(6 comments)
https://review.coreboot.org/c/coreboot/+/33839/8/Documentation/mainboard/pro... File Documentation/mainboard/protectli/fw6.jpg:
PS8:
Yes, I guess
Done
https://review.coreboot.org/c/coreboot/+/33839/8/Documentation/mainboard/pro... File Documentation/mainboard/protectli/fw6.md:
https://review.coreboot.org/c/coreboot/+/33839/8/Documentation/mainboard/pro... PS8, Line 28: microcode
Capitalize?
Done
https://review.coreboot.org/c/coreboot/+/33839/8/Documentation/mainboard/pro... PS8, Line 31: graphics in BIOS
It should be SeaBIOS or a pre-OS. […]
Done
https://review.coreboot.org/c/coreboot/+/33839/8/Documentation/mainboard/pro... PS8, Line 38: The first supported
missing rest of sentence
Done
https://review.coreboot.org/c/coreboot/+/33839/8/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/Kconfig:
https://review.coreboot.org/c/coreboot/+/33839/8/src/mainboard/protectli/vau... PS8, Line 5: select BOARD_ROMSIZE_KB_8192 : select HAVE_ACPI_RESUME : select HAVE_ACPI_TABLES : select SOC_INTEL_KABYLAKE : select SUPERIO_ITE_IT8772F : select MAINBOARD_HAS_LIBGFXINIT : select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS : select SPI_FLASH_MACRONIX
alphabetize?
Done
https://review.coreboot.org/c/coreboot/+/33839/8/src/mainboard/protectli/vau... File src/mainboard/protectli/vault_kbl/acpi_tables.c:
PS8:
This can go away
Done
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 10:
Board status available: https://review.coreboot.org/cgit/board-status.git/tree/protectli/vault_kbl/4...
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 10:
Patch Set 10:
Board status available: https://review.coreboot.org/cgit/board-status.git/tree/protectli/vault_kbl/4...
Thank you, but please add a note to the board status commit message next time, where to get the commit from.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 10: Code-Review+1
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 10:
Patch Set 10:
Patch Set 10:
Board status available: https://review.coreboot.org/cgit/board-status.git/tree/protectli/vault_kbl/4...
Thank you, but please add a note to the board status commit message next time, where to get the commit from.
I intended to add a fresh board status right after merging. This one is purely for review purposes.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33839/10/MAINTAINERS File MAINTAINERS:
https://review.coreboot.org/c/coreboot/+/33839/10/MAINTAINERS@330 PS10, Line 330: F: src/mainboard/protectli/ Please put it into a separate commit.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33839/10/MAINTAINERS File MAINTAINERS:
https://review.coreboot.org/c/coreboot/+/33839/10/MAINTAINERS@330 PS10, Line 330: F: src/mainboard/protectli/
Please put it into a separate commit.
Why so?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 10: Code-Review+1
(6 comments)
https://review.coreboot.org/c/coreboot/+/33839/10/Documentation/mainboard/pr... File Documentation/mainboard/protectli/fw6.jpg:
PS10: Where's the flash chip? I wouldn't want to hear about people reflashing their MOSFETs
https://review.coreboot.org/c/coreboot/+/33839/10/Documentation/mainboard/pr... File Documentation/mainboard/protectli/fw6.md:
https://review.coreboot.org/c/coreboot/+/33839/10/Documentation/mainboard/pr... PS10, Line 25: by coreboot by *the* coreboot
https://review.coreboot.org/c/coreboot/+/33839/10/Documentation/mainboard/pr... PS10, Line 49: Use a clip Is the flash chip voltage rail isolated from the rest of the system with a diode?
https://review.coreboot.org/c/coreboot/+/33839/10/Documentation/mainboard/pr... PS10, Line 76: with VGA Option ROM : - HDMI port with libgfxinit This can go on a single line:
... with both libgfxinit and the VGA Option ROM
(yes, I put libgfxinit first on purpose)
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... File src/mainboard/protectli/vault_kbl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... PS10, Line 292: q Trailing `q` ?
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... File src/mainboard/protectli/vault_kbl/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... PS10, Line 30: #include "acpi/mainboard.asl" I don't think we want to include an empty file
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... File src/mainboard/protectli/vault_kbl/bootblock.c:
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... PS10, Line 14: CLKIN_DEV GPIO_DEV maybe?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 10:
I'm wondering why this message appears in the logs:
https://review.coreboot.org/cgit/board-status.git/tree/protectli/vault_kbl/4...
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 10: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... File src/mainboard/protectli/vault_kbl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... PS10, Line 100: .ac_loadline = 1030, : .dc_loadline = 1030, Can we use the values for these parameters from SoC code? as for Iccmax
https://github.com/coreboot/coreboot/blob/7a70a46ecc30decffbea0bb3ef8fee54b1...
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... File src/mainboard/protectli/vault_kbl/ramstage.c:
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... PS10, Line 26: params->GmmEnable = 0; disable it in the devicetree: device pci 08.0 off end # Gaussian Mixture Model
https://github.com/coreboot/coreboot/blob/23c1c4e153e8f1311b2e04a19a7e0c66d6...
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 10:
Patch Set 10:
I'm wondering why this message appears in the logs:
https://review.coreboot.org/cgit/board-status.git/tree/protectli/vault_kbl/4...
mPCIe WiFI card not connected. The port is being disabled by FSP most likely.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maxim Polyakov, Matt DeVillier, Paul Menzel, Angel Pons, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33839
to look at the new patch set (#11).
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
mb/protectli/vault_kbl: Add FW6 support
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 --- M Documentation/mainboard/index.md A Documentation/mainboard/protectli/fw6.jpg A Documentation/mainboard/protectli/fw6.md A src/mainboard/protectli/Kconfig A src/mainboard/protectli/Kconfig.name A src/mainboard/protectli/vault_kbl/Kconfig A src/mainboard/protectli/vault_kbl/Kconfig.name A src/mainboard/protectli/vault_kbl/Makefile.inc A src/mainboard/protectli/vault_kbl/acpi/ec.asl A src/mainboard/protectli/vault_kbl/acpi/superio.asl A src/mainboard/protectli/vault_kbl/board_info.txt A src/mainboard/protectli/vault_kbl/bootblock.c A src/mainboard/protectli/vault_kbl/data.vbt A src/mainboard/protectli/vault_kbl/devicetree.cb A src/mainboard/protectli/vault_kbl/dsdt.asl A src/mainboard/protectli/vault_kbl/gma-mainboard.ads A src/mainboard/protectli/vault_kbl/gpio.h A src/mainboard/protectli/vault_kbl/ramstage.c A src/mainboard/protectli/vault_kbl/romstage.c 19 files changed, 868 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33839/11
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 11:
(10 comments)
https://review.coreboot.org/c/coreboot/+/33839/10/Documentation/mainboard/pr... File Documentation/mainboard/protectli/fw6.jpg:
PS10:
Where's the flash chip? I wouldn't want to hear about people reflashing their MOSFETs
On the bottom side. Described in Documentation
https://review.coreboot.org/c/coreboot/+/33839/10/Documentation/mainboard/pr... File Documentation/mainboard/protectli/fw6.md:
https://review.coreboot.org/c/coreboot/+/33839/10/Documentation/mainboard/pr... PS10, Line 25: by coreboot
by *the* coreboot
Done
https://review.coreboot.org/c/coreboot/+/33839/10/Documentation/mainboard/pr... PS10, Line 49: Use a clip
Is the flash chip voltage rail isolated from the rest of the system with a diode?
Not, it is not.
https://review.coreboot.org/c/coreboot/+/33839/10/Documentation/mainboard/pr... PS10, Line 76: with VGA Option ROM : - HDMI port with libgfxinit
This can go on a single line: […]
Done
https://review.coreboot.org/c/coreboot/+/33839/10/MAINTAINERS File MAINTAINERS:
https://review.coreboot.org/c/coreboot/+/33839/10/MAINTAINERS@330 PS10, Line 330: F: src/mainboard/protectli/
Why so?
Done
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... File src/mainboard/protectli/vault_kbl/bootblock.c:
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... PS10, Line 14: CLKIN_DEV
GPIO_DEV maybe?
Done
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... File src/mainboard/protectli/vault_kbl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... PS10, Line 100: .ac_loadline = 1030, : .dc_loadline = 1030,
Can we use the values for these parameters from SoC code? as for Iccmax […]
Done
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... PS10, Line 292: q
Trailing `q` ?
Leftovers of hotkeys... Removed
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... File src/mainboard/protectli/vault_kbl/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... PS10, Line 30: #include "acpi/mainboard.asl"
I don't think we want to include an empty file
Done
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... File src/mainboard/protectli/vault_kbl/ramstage.c:
https://review.coreboot.org/c/coreboot/+/33839/10/src/mainboard/protectli/va... PS10, Line 26: params->GmmEnable = 0;
disable it in the devicetree: […]
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 11: Code-Review+1
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maxim Polyakov, Matt DeVillier, Paul Menzel, Angel Pons, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33839
to look at the new patch set (#12).
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
mb/protectli/vault_kbl: Add FW6 support
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 --- M Documentation/mainboard/index.md A Documentation/mainboard/protectli/fw6.jpg A Documentation/mainboard/protectli/fw6.md M src/mainboard/protectli/Kconfig A src/mainboard/protectli/vault_kbl/Kconfig A src/mainboard/protectli/vault_kbl/Kconfig.name A src/mainboard/protectli/vault_kbl/Makefile.inc A src/mainboard/protectli/vault_kbl/acpi/ec.asl A src/mainboard/protectli/vault_kbl/acpi/superio.asl A src/mainboard/protectli/vault_kbl/board_info.txt A src/mainboard/protectli/vault_kbl/bootblock.c A src/mainboard/protectli/vault_kbl/data.vbt A src/mainboard/protectli/vault_kbl/devicetree.cb A src/mainboard/protectli/vault_kbl/dsdt.asl A src/mainboard/protectli/vault_kbl/gma-mainboard.ads A src/mainboard/protectli/vault_kbl/gpio.h A src/mainboard/protectli/vault_kbl/ramstage.c A src/mainboard/protectli/vault_kbl/romstage.c 18 files changed, 847 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33839/12
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 12: Code-Review+2
I think it's good to go. Thank you!
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 12: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/33839/12/Documentation/mainboard/pr... File Documentation/mainboard/protectli/fw6.md:
https://review.coreboot.org/c/coreboot/+/33839/12/Documentation/mainboard/pr... PS12, Line 55: with jumper or disconnect coin cell temporarily. Only then the platform will temporary
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33839/12/Documentation/mainboard/pr... File Documentation/mainboard/protectli/fw6.md:
https://review.coreboot.org/c/coreboot/+/33839/12/Documentation/mainboard/pr... PS12, Line 55: with jumper or disconnect coin cell temporarily. Only then the platform will
temporary
Why? Shouldn't it be an adverb?
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33839/12/Documentation/mainboard/pr... File Documentation/mainboard/protectli/fw6.md:
https://review.coreboot.org/c/coreboot/+/33839/12/Documentation/mainboard/pr... PS12, Line 55: with jumper or disconnect coin cell temporarily. Only then the platform will
Why? Shouldn't it be an adverb?
it's correct as-is.
if one wished to nit, it would be for the phrasing of the subsequent sentence (move 'will' after 'then') :)
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33839/12/Documentation/mainboard/pr... File Documentation/mainboard/protectli/fw6.md:
https://review.coreboot.org/c/coreboot/+/33839/12/Documentation/mainboard/pr... PS12, Line 55: with jumper or disconnect coin cell temporarily. Only then the platform will
Why? Shouldn't it be an adverb?
Temporarily=for a brief period of time. Adjective would be incorrect IMO: https://wikidiff.com/temporary/temporarily
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33839/12/Documentation/mainboard/pr... File Documentation/mainboard/protectli/fw6.md:
https://review.coreboot.org/c/coreboot/+/33839/12/Documentation/mainboard/pr... PS12, Line 55: with jumper or disconnect coin cell temporarily. Only then the platform will
Temporarily=for a brief period of time. Adjective would be incorrect IMO: […]
Ack
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33839/12/Documentation/mainboard/pr... File Documentation/mainboard/protectli/fw6.md:
https://review.coreboot.org/c/coreboot/+/33839/12/Documentation/mainboard/pr... PS12, Line 55: with jumper or disconnect coin cell temporarily. Only then the platform will
Ack
Agree (after re-read)
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/33839 )
Change subject: mb/protectli/vault_kbl: Add FW6 support ......................................................................
mb/protectli/vault_kbl: Add FW6 support
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33839 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Frans Hendriks fhendriks@eltan.com --- M Documentation/mainboard/index.md A Documentation/mainboard/protectli/fw6.jpg A Documentation/mainboard/protectli/fw6.md M src/mainboard/protectli/Kconfig A src/mainboard/protectli/vault_kbl/Kconfig A src/mainboard/protectli/vault_kbl/Kconfig.name A src/mainboard/protectli/vault_kbl/Makefile.inc A src/mainboard/protectli/vault_kbl/acpi/ec.asl A src/mainboard/protectli/vault_kbl/acpi/superio.asl A src/mainboard/protectli/vault_kbl/board_info.txt A src/mainboard/protectli/vault_kbl/bootblock.c A src/mainboard/protectli/vault_kbl/data.vbt A src/mainboard/protectli/vault_kbl/devicetree.cb A src/mainboard/protectli/vault_kbl/dsdt.asl A src/mainboard/protectli/vault_kbl/gma-mainboard.ads A src/mainboard/protectli/vault_kbl/gpio.h A src/mainboard/protectli/vault_kbl/ramstage.c A src/mainboard/protectli/vault_kbl/romstage.c 18 files changed, 847 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index c509c96..11f964f 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -120,6 +120,7 @@ ## Protectli
- [FW2B / FW4B](protectli/fw2b_fw4b.md) +- [FW6A / FW6B / FW6C](protectli/fw6.md)
## Roda
diff --git a/Documentation/mainboard/protectli/fw6.jpg b/Documentation/mainboard/protectli/fw6.jpg new file mode 100644 index 0000000..0c0b46d --- /dev/null +++ b/Documentation/mainboard/protectli/fw6.jpg Binary files differ diff --git a/Documentation/mainboard/protectli/fw6.md b/Documentation/mainboard/protectli/fw6.md new file mode 100644 index 0000000..86449d1 --- /dev/null +++ b/Documentation/mainboard/protectli/fw6.md @@ -0,0 +1,137 @@ +# Protectli Vault FW6 series + +This page describes how to run coreboot on the [Protectli FW6]. + + + +## Required proprietary blobs + +To build a minimal working coreboot image some blobs are required (assuming +only the BIOS region is being modified). + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+=====================+ +| FSP-M, FSP-S | Intel Firmware Support Package | Required | ++-----------------+---------------------------------+---------------------+ +| microcode | CPU microcode | Required | ++-----------------+---------------------------------+---------------------+ +| vgabios | VGA Option ROM | Optional | ++-----------------+---------------------------------+---------------------+ +``` + +FSP-M and FSP-S are obtained after splitting the Kaby Lake FSP binary (done +automatically by the coreboot build system and included into the image) from +the `3rdparty/fsp` submodule. + +Microcode updates are automatically included into the coreboot image by build +system from the `3rdparty/intel-microcode` submodule. + +VGA Option ROM is not required to boot, but if one needs graphics in pre-OS +stage, it should be included (if not using libgfxinit). + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. The first version +supporting the chipset is flashrom v1.1. Firmware an be easily flashed +with internal programmer (either BIOS region or full image). + +### External programming + +The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. +This chip is located on the bottom side of the case (the radiator side). One +has to remove all screws (in order): 4 top cover screws, 4 side cover screws +(one side is enough), 4 mainboard screws, 4 CPU screws (under DIMMs). Lift up +the mainboard and turn around it. The flash chip is near the SoC on the DIMM +slots side. Use a clip (or solder the wires) to program the chip. Specifically, +it's a Macronix MX25L6406E (3.3V) -[datasheet][MX25L6406E]. + +## Known issues + +- After flashing with external programmer it is always required to reset RTC + with jumper or disconnect coin cell temporarily. Only then the platform will + boot after flashing. +- FW6A does not always work reliably with all DIMMs. Linux happens to hang or + gives many panics. This issue was present also with vendor BIOS. +- Sometimes FSPMemoryInit return errors or hangs (especially with 2 DIMMs + connected). A workaround is to power cycle the board (even a few times) or + temporarily disconnect DIMM when platform is powered off. +- When using libgfxinit and SeaBIOS bootsplash, the red color is dim + +## Untested + +Not all mainboard's peripherals and functions were tested because of lack of +the cables or not being populated on the board case. + +- Internal USB 2.0 headers +- Boot with cleaned ME + +## Working + +- USB 3.0 front ports (SeaBIOS and Linux) +- 6 Ethernet ports +- HDMI port with libgfxinit and VGA Option ROM +- flashrom +- PCIe WiFi +- SATA and mSATA +- Super I/O serial port 0 (RS232 via front RJ45 connector) +- SMBus (reading SPD from DIMMs) +- Initialization with KBL FSP 2.0 (with MemoryInit issues) +- SeaBIOS payload (version rel-1.12.1) +- Mini PCIe debug card connected to mSATA (mSATA slot has LPC signals routed) +- Reset switch +- Booting Debian, Ubuntu, FreeBSD + +## Technology + +There are 3 variants of FW6 boards: FW6A, FW6B and FW6C. They differ only in +used SoC. + +- FW6A: + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Celeron 3865U | ++------------------+--------------------------------------------------+ +| PCH | Kaby Lake U w/ iHDCP2.2 Base | ++------------------+--------------------------------------------------+ +| Super I/O, EC | ITE IT8772E | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +- FW6B: + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Core i3-7100U | ++------------------+--------------------------------------------------+ +| PCH | Kaby Lake U w/ iHDCP2.2 Premium | ++------------------+--------------------------------------------------+ +| Super I/O, EC | ITE IT8772E | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +- FW6C: + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Core i5-7200U | ++------------------+--------------------------------------------------+ +| PCH | Kaby Lake U w/ iHDCP2.2 Premium | ++------------------+--------------------------------------------------+ +| Super I/O, EC | ITE IT8772E | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[Protectli FW6]: https://protectli.com/vault-6-port/ +[MX25L6406E]: https://www.macronix.com/Lists/Datasheet/Attachments/7370/MX25L6406E,%203V,%... +[flashrom]: https://flashrom.org/Flashrom diff --git a/src/mainboard/protectli/Kconfig b/src/mainboard/protectli/Kconfig index 3a1b7a4..1b4152e 100644 --- a/src/mainboard/protectli/Kconfig +++ b/src/mainboard/protectli/Kconfig @@ -10,7 +10,6 @@ source "src/mainboard/protectli/*/Kconfig"
config MAINBOARD_VENDOR - string "Mainboard Vendor" default "Protectli"
endif # VENDOR_PROTECTLI diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig new file mode 100644 index 0000000..bfafc0b --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/Kconfig @@ -0,0 +1,59 @@ +if BOARD_PROTECTLI_FW6 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select SOC_INTEL_KABYLAKE + select SPI_FLASH_MACRONIX + select SUPERIO_ITE_IT8772F + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "protectli/vault_kbl" + +config MAINBOARD_PART_NUMBER + string + default "FW6" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config MAX_CPUS + int + default 4 + +config VGA_BIOS_ID + string + default "8086,5916" # 8086,5906 for FW6A + +config PXE_ROM_ID + string + default "8086,150c" + +config CBFS_SIZE + hex + default 0x600000 + +config ADD_FSP_BINARIES + bool + default y + +config FSP_USE_REPO + bool + default y + +endif diff --git a/src/mainboard/protectli/vault_kbl/Kconfig.name b/src/mainboard/protectli/vault_kbl/Kconfig.name new file mode 100644 index 0000000..51a537a --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_PROTECTLI_FW6 + bool "FW6" diff --git a/src/mainboard/protectli/vault_kbl/Makefile.inc b/src/mainboard/protectli/vault_kbl/Makefile.inc new file mode 100644 index 0000000..d738748 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This file is part of the coreboot project. + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/protectli/vault_kbl/acpi/ec.asl b/src/mainboard/protectli/vault_kbl/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/acpi/ec.asl diff --git a/src/mainboard/protectli/vault_kbl/acpi/superio.asl b/src/mainboard/protectli/vault_kbl/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/acpi/superio.asl diff --git a/src/mainboard/protectli/vault_kbl/board_info.txt b/src/mainboard/protectli/vault_kbl/board_info.txt new file mode 100644 index 0000000..70bd174 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Protectli +Board name: FW6A/FW6B/FW6C +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/protectli/vault_kbl/bootblock.c b/src/mainboard/protectli/vault_kbl/bootblock.c new file mode 100644 index 0000000..125f9bf --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/bootblock.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <bootblock_common.h> +#include <superio/ite/it8772f/it8772f.h> +#include <superio/ite/common/ite.h> + +#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8772F_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_3vsbsw(GPIO_DEV); + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/protectli/vault_kbl/data.vbt b/src/mainboard/protectli/vault_kbl/data.vbt new file mode 100644 index 0000000..4379ed1 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/data.vbt Binary files differ diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb new file mode 100644 index 0000000..d53e43e --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -0,0 +1,309 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + register "s0ix_enable" = "1" + + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c03e1" + register "gen4_dec" = "0x001c02e1" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + register "eist_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # Enable VT-d + register "ignore_vtd" = "0" + + # Enable SERIRQ continuous + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "tcc_offset" = "5" # TCC of 95C + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPwrOptEnable" = "1" + register "EnableAzalia" = "0" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "0" + register "HeciEnabled" = "1" + register "PmTimerDisabled" = "1" + register "SaGv" = "SaGv_Enabled" + register "SaImguEnable" = "0" + register "IslVrCmd" = "2" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "4" # 4s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable SATA ports 1,2 + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "0" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + + # Enable Root ports. 1-6 for LAN and Root Port 9 + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[8]" = "1" # mPCIe WiFi + + # Enable Advanced Error Reporting for RP 1-6, 9 + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpAdvancedErrorReporting[1]" = "1" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + + # Enable Latency Tolerance Reporting Mechanism RP 1-6, 9 + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[1]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + # Enable RP 9 CLKREQ# support + register "PcieRpClkReqSupport[8]" = "1" + # RP 9 uses CLKREQ0# + register "PcieRpClkReqNumber[8]" = "0" + + # Clocks 0-5 for RP 1-6 + register "PcieRpClkSrcNumber[0]" = "0" + register "PcieRpClkSrcNumber[1]" = "1" + register "PcieRpClkSrcNumber[2]" = "2" + register "PcieRpClkSrcNumber[3]" = "3" + register "PcieRpClkSrcNumber[4]" = "4" + register "PcieRpClkSrcNumber[5]" = "5" + # RP 9 shares CLKSRC5# with RP 6 + register "PcieRpClkSrcNumber[8]" = "5" + + + # USB 2.0 enable ports 1-8, disable ports 9-12 + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disabled + + # USB 3.0 enable ports 1-4, disable ports 5-6 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled + + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Lock Down CHIPSET_LOCKDOWN_COREBOOT + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 08.0 off end # Gaussian Mixture Model + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # Thermal Subsystem + device pci 14.3 off end # Camera I/O Host Controller + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 on end # PCI Express Port 2 + device pci 1c.2 on end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 - WiFi + smbios_slot_desc + "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + chip superio/ite/it8772f + register "peci_tmpin" = "3" + register "tmpin1_mode" = "THERMAL_RESISTOR" + register "tmpin2_mode" = "THERMAL_RESISTOR" + # FAN2 available on fan header but unused + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa40 + io 0x62 = 0xa30 + irq 0x70 = 9 + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # IR + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/protectli/vault_kbl/dsdt.asl b/src/mainboard/protectli/vault_kbl/dsdt.asl new file mode 100644 index 0000000..624806c --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <soc/intel/skylake/acpi/platform.asl> + #include <soc/intel/skylake/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/protectli/vault_kbl/gma-mainboard.ads b/src/mainboard/protectli/vault_kbl/gma-mainboard.ads new file mode 100644 index 0000000..b7cae78 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/protectli/vault_kbl/gpio.h b/src/mainboard/protectli/vault_kbl/gpio.h new file mode 100644 index 0000000..3397d79 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/gpio.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#ifndef _GPIOFW6B_H +#define _GPIOFW6B_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PIRQA_N*/ PAD_CFG_TERM_GPO(GPP_A7, 1, NONE, DEEP), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), +/* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), +/* PME# */ PAD_CFG_NF(GPP_A11, 20K_PU, DEEP, NF1), +/* ISH_GP6 */ PAD_NC(GPP_A12, NONE), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PCH_SUSSTAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT_N */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0_N */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ1_N*/ PAD_NC(GPP_B6, NONE), +/* SRCCLKREQ2_N*/ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3_N*/ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4_N*/ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5_N*/ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE_N */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1), +/* GSPI0_CS_N */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS_N */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), +/* SML0_CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_CTS_N */ PAD_NC(GPP_C10, NONE), +/* UART0_RTS_N */ PAD_NC(GPP_C11, NONE), +/* UART1_RXD */ PAD_NC(GPP_C12, NONE), +/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_CTS_N */ PAD_NC(GPP_C14, NONE), +/* UART1_RTS_N */ PAD_NC(GPP_C15, NONE), +/* I2C0_SDA */ PAD_NC(GPP_C16, NONE), +/* I2C0_SCL */ PAD_NC(GPP_C17, NONE), +/* I2C1_SDA */ PAD_NC(GPP_C18, NONE), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), +/* UART2_RXD */ PAD_NC(GPP_C20, NONE), +/* UART2_TXD */ PAD_NC(GPP_C21, NONE), +/* UART2_CTS_N */ PAD_NC(GPP_C22, NONE), +/* UART2_RTS_N */ PAD_NC(GPP_C23, NONE), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* FLASHTRIG */ PAD_NC(GPP_D4, NONE), +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* GPP_D9 */ PAD_NC(GPP_D9, NONE), +/* GPP_D10 */ PAD_NC(GPP_D10, NONE), +/* GPP_D11 */ PAD_NC(GPP_D11, NONE), +/* GPP_D12 */ PAD_NC(GPP_D12, NONE), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK_1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA_1 */ PAD_NC(GPP_D18, NONE), +/* DMIC_CLK_0 */ PAD_NC(GPP_D19, NONE), +/* DMIC_DATA_0 */ PAD_NC(GPP_D20, NONE), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), +/* I2S_MCLK */ PAD_NC(GPP_D23, NONE), +/* SATAXPCIE0 (TP8) */ PAD_NC(GPP_E0, NONE), +/* SATAXPCIE1 (TP9)*/ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 (TP10) */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_NC(GPP_E7, NONE), +/* SATA_LED */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_NC(GPP_E9, NONE), +/* USB2_OC_1 */ PAD_NC(GPP_E10, NONE), +/* USB2_OC_2 */ PAD_NC(GPP_E11, NONE), +/* USB2_OC_3 */ PAD_NC(GPP_E12, NONE), +/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDI2_HPD */ PAD_NC(GPP_E14, NONE), +/* DDI3_HPD */ PAD_NC(GPP_E15, NONE), +/* DDI4_HPD */ PAD_NC(GPP_E16, NONE), +/* EDP_HPD */ PAD_NC(GPP_E17, NONE), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F9, NONE), +/* I2C5_SDA */ PAD_NC(GPP_F10, NONE), +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* GPP_F23 */ PAD_NC(GPP_F23, NONE), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), +/* PCH_BATLOW */ PAD_NC(GPD0, NONE), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* LAN_WAKE_N */ PAD_NC(GPD2, NONE), +/* PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# (TP7) */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* GPD7_RSVD */ PAD_CFG_TERM_GPO(GPD7, 1, NONE, DEEP), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* SLP_WLAN# (TP6) */ PAD_NC(GPD9, NONE), +/* SLP_S5# (TP3) */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_NC(GPD11, NONE), +}; + +#endif + +#endif diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/ramstage.c new file mode 100644 index 0000000..e9273ba --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/ramstage.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <bootstate.h> +#include <soc/ramstage.h> + +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* + * Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. + */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->TurboMode = 1; + params->PchThermalDeviceEnable = 0; + params->PchPort61hEnable = 1; + params->CdClock = 3; +} diff --git a/src/mainboard/protectli/vault_kbl/romstage.c b/src/mainboard/protectli/vault_kbl/romstage.c new file mode 100644 index 0000000..e65151b --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/romstage.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) +{ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) +{ + const u8 dqs_map[2][8] = { + { 0, 1, 2, 3, 4, 5, 6, 7 }, + { 1, 0, 2, 3, 4, 5, 6, 7 } }; + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + static const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + struct spd_block blk = { + .addr_map = { 0x50, 0x52, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +}
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