the following patch was just integrated into master: commit a09760eb451466c7972614ef9d73752e16a1bf69 Author: Aaron Durbin adurbin@chromium.org Date: Tue Mar 26 13:34:37 2013 -0500
libpayload: add x86 ROM variable MTRR support
On x86, coreboot may allocate a variable range MTRR for enabling caching of the system ROM. Add the ability to parse this structure and add the result to the sysinfo structure.
An example usage implementation would be to obtain the variable MTRR index that covers the ROM from the sysinfo structure. Then one would disable caching and change the MTRR type from uncacheable to write-protect and enable caching. The opposite sequence is required to tearn down the caching.
Change-Id: I3bfe2028d8574d3adb1d85292abf8f1372cf97fa Signed-off-by: Aaron Durbin adurbin@chromium.org Reviewed-on: http://review.coreboot.org/2920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer stefan.reinauer@coreboot.org
Build-Tested: build bot (Jenkins) at Fri Mar 29 15:02:19 2013, giving +1 Reviewed-By: Stefan Reinauer stefan.reinauer@coreboot.org at Fri Mar 29 20:10:14 2013, giving +2 See http://review.coreboot.org/2920 for details.
-gerrit