Change in coreboot[master]: soc/amd/common/block/acpimmio/print_reset_status: add missing status bit

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60184 )

Change subject: soc/amd/common/block/acpimmio/print_reset_status: add missing status bit
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soc/amd/common/block/acpimmio/print_reset_status: add missing status bit

Both the Picasso PPR #55570 Rev 3.18 and the Cezanne PPR #56569 Rev 3.03
define bit 9 of the PM_RST_STATUS register as internal Thermal Trip
reset status bit.

Signed-off-by: Felix Held 
Change-Id: Ida8b13fe62b16c18fc9924520b83220e73eca624
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60184
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
Reviewed-by: Jason Glenesk 
Reviewed-by: Paul Menzel 
---
M src/soc/amd/common/block/acpimmio/print_reset_status.c
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Raul Rangel: Looks good to me, approved
  Jason Glenesk: Looks good to me, but someone else must approve

diff --git a/src/soc/amd/common/block/acpimmio/print_reset_status.c b/src/soc/amd/common/block/acpimmio/print_reset_status.c
index 3825753..309401e 100644
--- a/src/soc/amd/common/block/acpimmio/print_reset_status.c
+++ b/src/soc/amd/common/block/acpimmio/print_reset_status.c
@@ -33,6 +33,7 @@
    	[3] = "ThermalTripFromTemp",
    	[4] = "RemotePowerDownFromASF",
    	[5] = "ShutDownFan0",
+		[9] = "InternalThermalTrip",
    	[16] = "UserRst",
    	[17] = "SoftPciRst",
    	[18] = "DoInit",