Patch set updated for coreboot: amd/pi/hudson: Add SPI definitions to header

[Marshall Dawson]

Marshall Dawson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18441

-gerrit

commit 6762be1d46e79b73591ab0933f95f9dbb81fb5f4
Author: Marshall Dawson 
Date:   Sun Jan 29 17:29:46 2017 -0700

amd/pi/hudson: Add SPI definitions to header

Add defines that will be used later for setting the fastest settings
    in the SPI controller.

Original-Signed-off-by: Marshall Dawson 
    Original-Reviewed-by: Marc Jones 
    (cherry picked from commit 0d2c28b8156dcc1f3dc925b3c3ba15b6b07f202c)

Change-Id: I660cc9ed6910c33042321c80453c7f74912455d9
    Signed-off-by: Marc Jones 
---
 src/southbridge/amd/pi/hudson/hudson.h | 38 ++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index fc37467..cb0f273 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -86,6 +86,44 @@
 #define DECODE_ENABLE_ACPIUC_PORT     BIT(30)
 #define DECODE_ENABLE_ADLIB_PORT      BIT(31)

+#define SPI_CNTRL0                    0x00
+#define SPI_READ_MODE_MASK            (BIT(30) | BIT(29) | BIT(18))
+/* Nominal is 16.7MHz on older devices, 33MHz on newer */
+#define SPI_READ_MODE_NOM             0x00000000
+#define SPI_READ_MODE_DUAL112         (          BIT(29)          )
+#define SPI_READ_MODE_QUAD114         (          BIT(29) | BIT(18))
+#define SPI_READ_MODE_DUAL122         (BIT(30)                    )
+#define SPI_READ_MODE_QUAD144         (BIT(30) |           BIT(18))
+#define SPI_READ_MODE_NORMAL66        (BIT(30) | BIT(29)          )
+/* Nominal and SPI_READ_MODE_FAST_HUDSON1 are the only valid choices for H1 */
+#define SPI_READ_MODE_FAST_HUDSON1    (                    BIT(18))
+#define SPI_READ_MODE_FAST            (BIT(30) | BIT(29) | BIT(18))
+#define SPI_ARB_ENABLE                BIT(19)
+
+#define SPI_CNTRL1                    0x0c
+/* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */
+#define SPI_CNTRL1_SPEED_MASK         (BIT(15) | BIT(14) | BIT(13) | BIT(12))
+#define SPI_NORM_SPEED_SH             12
+#define SPI_FAST_SPEED_SH             8
+
+#define SPI100_ENABLE                 0x20
+#define SPI_USE_SPI100                BIT(0)
+
+#define SPI100_SPEED_CONFIG           0x22
+#define SPI_SPEED_66M                 (0x0)
+#define SPI_SPEED_33M                 (                  BIT(0))
+#define SPI_SPEED_22M                 (         BIT(1)         )
+#define SPI_SPEED_16M                 (         BIT(1) | BIT(0))
+#define SPI_SPEED_100M                (BIT(2)                  )
+#define SPI_SPEED_800K                (BIT(2) |          BIT(0))
+#define SPI_NORM_SPEED_NEW_SH         12
+#define SPI_FAST_SPEED_NEW_SH         8
+#define SPI_ALT_SPEED_NEW_SH          4
+#define SPI_TPM_SPEED_NEW_SH          0
+
+#define SPI100_HOST_PREF_CONFIG       0x2c
+#define SPI_RD4DW_EN_HOST             BIT(15)
+
 static inline int hudson_sata_enable(void)
 {
    /* True if IDE or AHCI. */