Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
mb/google/dedede/var/magolor: apply DPTF setting
add the tcc, critical, passive policy, and pl values
BUG=b:168353037 TEST=build and verify by thermal tool
Change-Id: I887d494ff097a881d519a456f24578a278323051 Signed-off-by: Ren Kuo ren.kuo@quanta.corp-partner.google.com --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/45453/1
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 0daaea3..3a61981 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -40,7 +40,49 @@ }, }"
+ register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "tcc_offset" = "15" # TCC of 90C + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 6000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000)" + + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 7000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 7000, + .max_power = 12000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 3000 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + device generic 0 on end + end + end # SA Thermal device device pci 05.0 on # IPU - MIPI Camera chip drivers/intel/mipi_camera register "acpi_uid" = "0x50000"
Ren Kuo has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
mb/google/dedede/var/magolor: apply DPTF setting
add tcc, critical, passive policy, and pl values
BUG=b:168353037 TEST=build and verify by thermal tool
Change-Id: I887d494ff097a881d519a456f24578a278323051 Signed-off-by: Ren Kuo ren.kuo@quanta.corp-partner.google.com --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/45453/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45453/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45453/2//COMMIT_MSG@9 PS2, Line 9: add tcc, critical, passive policy, and pl values Received from whom?
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45453/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/magolor/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45453/2/src/mainboard/google/dedede... PS2, Line 44: .tdp_pl1_override = 7, : .tdp_pl2_override = 12, Sumeet, Are these numbers fine. I see TDP for JSL is 6W. Shouldn't PL1 be 6 then?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45453/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/magolor/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45453/2/src/mainboard/google/dedede... PS2, Line 44: .tdp_pl1_override = 7, : .tdp_pl2_override = 12,
Sumeet, Are these numbers fine. I see TDP for JSL is 6W. […]
7W will be the default setting here, but DPTF can override it between 3 and 7W (see lines 65,66)
Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45453/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/magolor/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45453/2/src/mainboard/google/dedede... PS2, Line 44: .tdp_pl1_override = 7, : .tdp_pl2_override = 12,
7W will be the default setting here, but DPTF can override it between 3 and 7W (see lines 65,66)
agree!
Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45453/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/magolor/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45453/2/src/mainboard/google/dedede... PS2, Line 44: .tdp_pl1_override = 7, : .tdp_pl2_override = 12,
agree!
thermal engr. peter think that pl1 initial setting to 7w for good performance in previous development stage range: .min_power = 7000, .max_power = 12000,
if the thermal test is fail on EVT sample, Peter will tune the value down.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45453/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/magolor/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45453/2/src/mainboard/google/dedede... PS2, Line 44: .tdp_pl1_override = 7, : .tdp_pl2_override = 12,
thermal engr. […]
if this is the initial setting value and system thermal design support this value, in that case it might be ok.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
Patch Set 2: Code-Review+1
Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
Patch Set 3: Code-Review+1
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/45453/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/magolor/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45453/2/src/mainboard/google/dedede... PS2, Line 44: .tdp_pl1_override = 7, : .tdp_pl2_override = 12,
if this is the initial setting value and system thermal design support this value, in that case it m […]
Done
Hello build bot (Jenkins), Furquan Shaikh, Henry Sun, Tim Wawrzynczak, Sumeet R Pawnikar, Marco Chen, Karthik Ramasubramanian, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45453
to look at the new patch set (#4).
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
mb/google/dedede/var/magolor: apply DPTF setting
add tcc, critical, passive policy, and pl values from thermal team
BUG=b:168353037 TEST=build and verify by thermal tool
Change-Id: I887d494ff097a881d519a456f24578a278323051 Signed-off-by: Ren Kuo ren.kuo@quanta.corp-partner.google.com --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/45453/4
Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45453/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45453/2//COMMIT_MSG@9 PS2, Line 9: add tcc, critical, passive policy, and pl values
Received from whom?
done! peter.ou@quanta.corp-partner.google.com provided the data.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
Patch Set 4: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/45453/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45453/2//COMMIT_MSG@9 PS2, Line 9: add tcc, critical, passive policy, and pl values
done! peter.ou@quanta.corp-partner.google.com […]
Thanks, this looks fine and can be merge.
Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45453/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45453/2//COMMIT_MSG@9 PS2, Line 9: add tcc, critical, passive policy, and pl values
Thanks, this looks fine and can be merge.
Ok
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45453 )
Change subject: mb/google/dedede/var/magolor: apply DPTF setting ......................................................................
mb/google/dedede/var/magolor: apply DPTF setting
add tcc, critical, passive policy, and pl values from thermal team
BUG=b:168353037 TEST=build and verify by thermal tool
Change-Id: I887d494ff097a881d519a456f24578a278323051 Signed-off-by: Ren Kuo ren.kuo@quanta.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45453 Reviewed-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Reviewed-by: Karthik Ramasubramanian kramasub@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 42 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Ren Kuo: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 496623c..8a83b83 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -40,7 +40,49 @@ }, }"
+ register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "tcc_offset" = "15" # TCC of 90C + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 6000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000)" + + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 7000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 7000, + .max_power = 12000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 3000 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + device generic 0 on end + end + end # SA Thermal device device pci 05.0 on # IPU - MIPI Camera chip drivers/intel/mipi_camera register "acpi_uid" = "0x50000"