Change in coreboot[master]: mb/google/brya/var/felwinter: Disable PCIE port 6

[EricR Lai (Code Review)]

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59243 )

Change subject: mb/google/brya/var/felwinter: Disable PCIE port 6
......................................................................

mb/google/brya/var/felwinter: Disable PCIE port 6

PCIE port 6 is empty as shcematics.

BUG=b:206047996
TEST=PCIE port 6 is disabled.

Signed-off-by: Eric Lai 
Change-Id: I30fa897c9310c44545e3df670895639a5144e1de
---
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/59243/1

diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index 4647551..ad470a8 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -59,6 +59,7 @@
    			end
    		end
    	end
+		device ref pcie_rp6 off end
    	device ref pcie_rp8 on
    		chip soc/intel/common/block/pcie/rtd3
    			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"