Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40117 )
Change subject: sb/intel/ibexpeak: Do some cosmetic fixes ......................................................................
sb/intel/ibexpeak: Do some cosmetic fixes
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I3474213efa05a11ce01e3d274db5941d1a847128 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/bootblock.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/early_thermal.c M src/southbridge/intel/ibexpeak/early_usb.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/madt.c M src/southbridge/intel/ibexpeak/me.h M src/southbridge/intel/ibexpeak/nvs.h M src/southbridge/intel/ibexpeak/pch.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c 16 files changed, 315 insertions(+), 333 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/40117/1
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index fe5cc2e..12c7bc8 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -63,11 +63,11 @@ if (set_bits(base + 0x08, 1, 1) == -1) goto no_codec;
- /* Write back the value once reset bit is set. */ + /* Write back the value once reset bit is set */ write16(base + 0x0, read16(base + 0x0));
- /* Read in Codec location (BAR + 0xe)[2..0]*/ + /* Read in Codec location (BAR + 0xe)[2..0] */ reg8 = read8(base + 0xe); reg8 &= 0x0f; if (!reg8) @@ -102,10 +102,9 @@ }
/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative + * Wait 50usec for the codec to indicate that it is ready. + * No response would imply that the codec is non-operative. */ - static int wait_for_ready(u8 *base) { /* Use a 1msec timeout */ @@ -123,11 +122,9 @@ }
/** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the codec is non-operative. */ - static int wait_for_valid(u8 *base) { u32 reg32; @@ -142,9 +139,9 @@ int timeout = 1000; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; + udelay(1); }
@@ -232,8 +229,8 @@ if (!res) return;
- // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? + // NOTE this will break as soon as the Azalia gets a bar above 4G. + // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
@@ -259,7 +256,7 @@ reg32 |= (1 << 31); pci_write_config32(dev, 0x120, reg32);
- // Enable HDMI codec: + // Enable HDMI codec reg32 = pci_read_config32(dev, 0xc4); reg32 |= (1 << 1); pci_write_config32(dev, 0xc4, reg32); @@ -319,7 +316,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &azalia_pci_ops, };
@@ -327,11 +324,11 @@ 0x1c20, 0x1e20, PCI_DID_INTEL_IBEXPEAK_AUDIO, - 0 + 0, };
static const struct pci_driver pch_azalia __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_INTEL, + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 82cb29f..3607f6b 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -72,10 +72,10 @@ * - 0x208-0x20f GAMEH * - 0x200-0x207 GAMEL */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN - | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN - | COMB_LPC_EN | COMA_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_EN, + GAMEL_LPC_EN | CNF1_LPC_EN | COMA_LPC_EN | FDD_LPC_EN | KBC_LPC_EN | + GAMEH_LPC_EN | CNF2_LPC_EN | COMB_LPC_EN | LPT_LPC_EN | MC_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
/* Clear PWR_FLR */ diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 00d5822..2947206 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -30,9 +30,11 @@
static void pch_default_disable(void) { - /* Must set BIT0 (hides performance counters PCI device). - coreboot enables the Rate Matching Hub which makes the UHCI PCI - devices disappear, so BIT5-12 and BIT28 can be set to hide those. */ + /* + * Must set BIT0 (hides performance counters PCI device). + * coreboot enables the Rate Matching Hub which makes the UHCI PCI devices disappear, + * so BIT5-12 and BIT28 can be set to hide those. + */ RCBA32(FD) = (1 << 28) | (0xff << 5) | 1;
/* Set reserved bit to 1 */ @@ -43,8 +45,10 @@ { early_gpio_init(); enable_smbus(); - /* TODO, make this configurable */ + + /* TODO: make this configurable */ pch_setup_cir(IRONLAKE_MOBILE); + southbridge_configure_default_intmap(); pch_default_disable(); early_usb_init(mainboard_usb_ports); diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index 4db81bc..7a1d1d4 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -13,9 +13,11 @@ * GNU General Public License for more details. */
-#include <device/pci_ops.h> #include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <device/smbus_host.h> + #include "pch.h"
uintptr_t smbus_base(void) @@ -26,15 +28,14 @@ int smbus_enable_iobar(uintptr_t base) { /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 3);
- /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) + /* Check to make sure we've got the right device */ + if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) return -1;
- /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); + /* Set SMBus I/O base */ + pci_write_config32(dev, SMB_BASE, base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index 2838db1..1ee7382 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -19,35 +19,37 @@ #include "cpu/intel/model_2065x/model_2065x.h" #include <cpu/x86/msr.h>
-/* Early thermal init, must be done prior to giving ME its memory - which is done at the end of raminit. */ +/* We use this temporary BAR to program some registers in the Thermal device's MMIO window */ +#define THERMAL_BASE (0x40000000) + +#define THERMAL16(x) ((u16 *)((THERMAL_BASE) + (x))) + +/* Early thermal init, must be done before giving ME its memory, which is done after raminit */ void early_thermal_init(void) { - pci_devfn_t dev; msr_t msr;
- dev = PCI_DEV(0x0, 0x1f, 0x6); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 6);
- /* Program address for temporary BAR. */ - pci_write_config32(dev, 0x40, 0x40000000); - pci_write_config32(dev, 0x44, 0x0); + /* Program address for temporary BAR */ + pci_write_config32(dev, 0x40, THERMAL_BASE); + pci_write_config32(dev, 0x44, 0);
- /* Activate temporary BAR. */ - pci_write_config32(dev, 0x40, - pci_read_config32(dev, 0x40) | 5); + /* Activate temporary BAR */ + pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5);
- /* Perform init. */ - /* Configure TJmax. */ + /* Perform init */ + /* Configure TJmax */ msr = rdmsr(MSR_TEMPERATURE_TARGET); - write16((u16 *)0x40000012, ((msr.lo >> 16) & 0xff) << 6); - /* Northbridge temperature slope and offset. */ - write16((u16 *)0x40000016, 0x7746); - /* Enable thermal data reporting, processor, PCH and northbridge. */ - write16((u16 *)0x4000001a, - (read16((u16 *)0x4000001a) & ~0xf) | 0x10f0); + write16(THERMAL16(0x12), ((msr.lo >> 16) & 0xff) << 6);
- /* Disable temporary BAR. */ - pci_write_config32(dev, 0x40, - pci_read_config32(dev, 0x40) & ~1); + /* Northbridge temperature slope and offset */ + write16(THERMAL16(0x16), 0x7746); + + /* Enable thermal data reporting, processor, PCH and northbridge */ + write16(THERMAL16(0x1a), (read16(THERMAL16(0x1a)) & ~0xf) | 0x10f0); + + /* Disable temporary BAR */ + pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1); pci_write_config32(dev, 0x40, 0); } diff --git a/src/southbridge/intel/ibexpeak/early_usb.c b/src/southbridge/intel/ibexpeak/early_usb.c index 4fdb1e5..c155123 100644 --- a/src/southbridge/intel/ibexpeak/early_usb.c +++ b/src/southbridge/intel/ibexpeak/early_usb.c @@ -27,8 +27,8 @@ void early_usb_init(const struct southbridge_usb_port *portmap) { u32 reg32; - const u16 currents[] = { 0xf57, 0xf5f, 0x753, 0x75f, 0x14b, 0x74b, - 0x557, 0x757, 0x55f, 0x54b + const u16 currents[] = { + 0x0f57, 0x0f5f, 0x0753, 0x075f, 0x014b, 0x074b, 0x0557, 0x0757, 0x055f, 0x054b, }; int i;
@@ -42,27 +42,32 @@ TODO maybe vendor firmware values are better? */ RCBA32(USBIRC) &= ~(1 << 8); RCBA32_OR(USBIRA, (7 << 12) | (7 << 8) | (7 << 4) | (2 << 0)); - RCBA32_AND_OR(USBIRB, ~0x617f0, (3 << 17) | (1 << 12) | (1 << 10) - | (1 << 8) | (4 << 4)); + + RCBA32_AND_OR(USBIRB, ~0x17f0, (3 << 17) | (1 << 12) | (1 << 10) | (1 << 8) | (4 << 4)); /* Set to Rate Matching Hub Mode to make PCI devices appear. */ RCBA32(0x3598) = 0;
reg32 = 0; - for (i = 0; i < TOTAL_USB_PORTS; i++) + for (i = 0; i < TOTAL_USB_PORTS; i++) { if (!portmap[i].enabled) reg32 |= (1 << i); + } RCBA32(USBPDO) = reg32; + reg32 = 0; /* The OC pins of the first 8 USB ports are mapped in USBOCM1 */ - for (i = 0; i < 8; i++) + for (i = 0; i < 8; i++) { if (portmap[i].enabled && portmap[i].oc_pin >= 0) reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); + } RCBA32(USBOCM1) = reg32; + reg32 = 0; /* The OC pins of the remainder 6 USB ports are mapped in USBOCM2 */ - for (i = 8; i < TOTAL_USB_PORTS; i++) + for (i = 8; i < TOTAL_USB_PORTS; i++) { if (portmap[i].enabled && portmap[i].oc_pin >= 4) reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); + } RCBA32(USBOCM2) = reg32;
/* Relock registers. */ diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 73f19c7..5ac3bb5 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -55,7 +55,7 @@ pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
set_ioapic_id(VIO_APIC_VADDR, 0x01); - /* affirm full set of redirection table entries ("write once") */ + /* Affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
@@ -69,11 +69,10 @@ static void pch_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit for one frame. */ - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + #if !CONFIG(SERIRQ_CONTINUOUS_MODE) - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif }
@@ -94,6 +93,7 @@ * 0x0D - 1101 = Reserved * 0x0E - 1110 = IRQ14 * 0x0F - 1111 = IRQ15 + * * PIRQ[n]_ROUT[7] - PIRQ Routing Control * 0x80 - The PIRQ is not routed. */ @@ -101,12 +101,12 @@ static void pch_pirq_init(struct device *dev) { struct device *irq_dev; - /* Interrupt 11 is not used by legacy devices and so can always be used for - PCI interrupts. Full legacy IRQ routing is complicated and hard to - get right. Fortunately all modern OS use MSI and so it's not that big of - an issue anyway. Still we have to provide a reasonable default. Using - interrupt 11 for it everywhere is a working default. ACPI-aware OS can - move it to any interrupt and others will just leave them at default. + /* + * Interrupt 11 is not used by legacy devices and so it can always be used for PCI + * interrupts. Full legacy IRQ routing is complicated and hard to get right. Fortunately + * all modern OSes use MSI and so it's not that big of an issue anyway. We still have to + * provide a reasonable default. Using interrupt 11 everywhere works, because ACPI-aware + * OSes can move it to any interrupt and others will just leave them at default. */ const u8 pirq_routing = 11;
@@ -121,7 +121,7 @@ pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0; + u8 int_pin = 0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) continue; @@ -141,19 +141,17 @@ config_t *config = dev->chip_info; u32 reg32 = 0;
- /* An array would be much nicer here, or some - * other method of doing this. - */ - reg32 |= (config->gpi0_routing & 0x03) << 0; - reg32 |= (config->gpi1_routing & 0x03) << 2; - reg32 |= (config->gpi2_routing & 0x03) << 4; - reg32 |= (config->gpi3_routing & 0x03) << 6; - reg32 |= (config->gpi4_routing & 0x03) << 8; - reg32 |= (config->gpi5_routing & 0x03) << 10; - reg32 |= (config->gpi6_routing & 0x03) << 12; - reg32 |= (config->gpi7_routing & 0x03) << 14; - reg32 |= (config->gpi8_routing & 0x03) << 16; - reg32 |= (config->gpi9_routing & 0x03) << 18; + /* An array would be much nicer here, or some other method of doing this. */ + reg32 |= (config->gpi0_routing & 0x03) << 0; + reg32 |= (config->gpi1_routing & 0x03) << 2; + reg32 |= (config->gpi2_routing & 0x03) << 4; + reg32 |= (config->gpi3_routing & 0x03) << 6; + reg32 |= (config->gpi4_routing & 0x03) << 8; + reg32 |= (config->gpi5_routing & 0x03) << 10; + reg32 |= (config->gpi6_routing & 0x03) << 12; + reg32 |= (config->gpi7_routing & 0x03) << 14; + reg32 |= (config->gpi8_routing & 0x03) << 16; + reg32 |= (config->gpi9_routing & 0x03) << 18; reg32 |= (config->gpi10_routing & 0x03) << 20; reg32 |= (config->gpi11_routing & 0x03) << 22; reg32 |= (config->gpi12_routing & 0x03) << 24; @@ -176,11 +174,12 @@ int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option;
- /* Which state do we want to goto after g3 (power restored)? + /* + * Which state do we want to go to after G3 (power restored)? * 0 == S0 Full On * 1 == S5 Soft Off * - * If the option is not existent (Laptops), use Kconfig setting. + * If the option is not present, use Kconfig setting. */ get_option(&pwr_on, "power_on_after_fail");
@@ -204,12 +203,11 @@ }
reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ - reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ + reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
reg16 &= ~(1 << 10); - reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ - - reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ + reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ + reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
pci_write_config16(dev, GEN_PMCON_3, reg16); printk(BIOS_INFO, "Set power %s after power failure.\n", state); @@ -219,7 +217,7 @@ reg8 &= 0x0f; /* Higher Nibble must be 0 */ reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ - reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + reg8 |= (1 << 2); /* PCI SERR# Disable for now */ outb(reg8, 0x61);
reg8 = inb(0x70); @@ -238,10 +236,9 @@ reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 &= ~(3 << 0); // SMI# rate 1 minute reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME + #if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using - * periodic SMIs. - */ + /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs. */ reg16 |= (3 << 0); // Periodic SMI every 8s #endif pci_write_config16(dev, GEN_PMCON_1, reg16); @@ -255,9 +252,9 @@ outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
/* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT - reg32 &= ~(7 << 10); // SLP_TYP - reg32 |= (1 << 0); // SCI_EN + reg32 = inl(pmbase + 0x04); // PM1_CNT + reg32 &= ~(7 << 10); // SLP_TYP + reg32 |= (1 << 0); // SCI_EN outl(reg32, pmbase + 0x04);
/* Clear magic status bits to prevent unexpected wake */ @@ -336,31 +333,28 @@ RCBA32 (0x2208) = 0x00003457; (void) RCBA32 (0x2208);
- const u32 rcba2210[] = - { - /* 2210 */ 0x00000000, 0x00000001, 0xa0fff210, 0x0000df00, - /* 2220 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, - /* 2230 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, - /* 2240 */ 0x00002301, 0x36000000, 0x00010107, 0x00160000, - /* 2250 */ 0x00001b01, 0x36000000, 0x00010107, 0x00160000, - /* 2260 */ 0x00000601, 0x16000000, 0x00010107, 0x00160000, - /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000 - }; + const u32 rcba2210[] = { + /* 2210 */ 0x00000000, 0x00000001, 0xa0fff210, 0x0000df00, + /* 2220 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, + /* 2230 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, + /* 2240 */ 0x00002301, 0x36000000, 0x00010107, 0x00160000, + /* 2250 */ 0x00001b01, 0x36000000, 0x00010107, 0x00160000, + /* 2260 */ 0x00000601, 0x16000000, 0x00010107, 0x00160000, + /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000, + };
- for (i = 0; i < sizeof(rcba2210) / sizeof(rcba2210[0]); i++) - { + for (i = 0; i < ARRAY_SIZE(rcba2210); i++) { RCBA32 (0x2210 + 4 * i) = rcba2210[i]; RCBA32 (0x2210 + 4 * i); }
- const u32 rcba2300[] = - { - /* 2300: */ 0x00000000, 0x40000000, 0x4646827b, 0x6e803131, - /* 2310: */ 0x32c77887, 0x00077733, 0x00007447, 0x00000040, - /* 2320: */ 0xcccc0cfc, 0x0fbb0fff - }; + const u32 rcba2300[] = { + /* 2300: */ 0x00000000, 0x40000000, 0x4646827b, 0x6e803131, + /* 2310: */ 0x32c77887, 0x00077733, 0x00007447, 0x00000040, + /* 2320: */ 0xcccc0cfc, 0x0fbb0fff, + };
- for (i = 0; i < sizeof(rcba2300) / sizeof(rcba2300[0]); i++) + for (i = 0; i < ARRAY_SIZE(rcba2300); i++) { RCBA32 (0x2300 + 4 * i) = rcba2300[i]; RCBA32 (0x2300 + 4 * i); @@ -384,7 +378,7 @@
/* Move HPET to default address 0xfed00000 and enable it */ reg32 = RCBA32(HPTC); - reg32 |= (1 << 7); // HPET Address Enable + reg32 |= (1 << 7); // HPET Address Enable reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; RCBA32(HPTC); /* Read back for it to work */ @@ -404,17 +398,18 @@ pci_write_config16(dev, GEN_PMCON_1, reg16);
reg32 = RCBA32(CG); - reg32 |= (1 << 31); - reg32 |= (1 << 29) | (1 << 28); - reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); - reg32 |= (1 << 16); - reg32 |= (1 << 17); - reg32 |= (1 << 18); - reg32 |= (1 << 22); - reg32 |= (1 << 23); + reg32 |= (1 << 31); + reg32 |= (1 << 29) | (1 << 28); + reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); + reg32 |= (1 << 16); + reg32 |= (1 << 17); + reg32 |= (1 << 18); + reg32 |= (1 << 22); + reg32 |= (1 << 23); reg32 &= ~(1 << 20); - reg32 |= (1 << 19); - reg32 |= (1 << 0); + reg32 |= (1 << 19); + reg32 |= (1 << 0); + reg32 |= (0xf << 1); RCBA32(CG) = reg32;
@@ -444,11 +439,9 @@
static void pch_fixups(struct device *dev) { - /* - * Enable DMI ASPM in the PCH - */ + /* Enable DMI ASPM in the PCH */ RCBA32_AND_OR(0x2304, ~(1 << 10), 0); - RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); + RCBA32_OR(0x21a4, (1 << 11) | (1 << 10)); RCBA32_OR(0x21a8, 0x3); }
@@ -501,6 +494,7 @@ pch_fixups(dev); }
+#define ASSIGNED_FIXED (IORESOURCE_ASSIGNED | IORESOURCE_FIXED) static void pch_lpc_read_resources(struct device *dev) { struct resource *res; @@ -514,51 +508,45 @@ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = 0; res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = 0xff800000; res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED;
res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_MEM | ASSIGNED_FIXED;
/* Set PCH IO decode ranges if required.*/ if ((config->gen1_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = config->gen1_dec & 0xFFFC; res->size = (config->gen1_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED; }
if ((config->gen2_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = config->gen2_dec & 0xFFFC; res->size = (config->gen2_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED; }
if ((config->gen3_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = config->gen3_dec & 0xFFFC; res->size = (config->gen3_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED; }
if ((config->gen4_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = config->gen4_dec & 0xFFFC; res->size = (config->gen4_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED; } }
@@ -603,53 +591,53 @@
fadt->reserved = 0;
- fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + fadt->s4bios_req = 0; + fadt->pstate_cnt = 0;
fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; + fadt->pm1b_evt_blk = 0; fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; + fadt->pm1b_cnt_blk = 0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0;
- fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + c2_latency = chip->c2_latency; if (!c2_latency) { c2_latency = 101; /* c2 unsupported */ } - fadt->p_lvl2_lat = c2_latency; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; + + fadt->p_lvl2_lat = c2_latency; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; fadt->flush_stride = 16; /* P_CNT not supported */ - fadt->duty_offset = 0; - fadt->duty_width = 0; + fadt->duty_offset = 0; + fadt->duty_width = 0;
fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; - fadt->century = 0x32; + fadt->century = 0x32; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
- fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; + fadt->flags = ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_WBINVD | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_S4_RTC_WAKE; + if (chip->docking_supported) { fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; } @@ -657,70 +645,70 @@ fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; }
- fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0;
fadt->reset_value = 6;
- fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0;
- fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; + fadt->x_pm1b_evt_blk.addrl = 0; + fadt->x_pm1b_evt_blk.addrh = 0;
- fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0;
- fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; + fadt->x_pm1b_cnt_blk.addrl = 0; + fadt->x_pm1b_cnt_blk.addrh = 0;
- fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0;
- fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0;
- fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0;
- fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0; }
static const char *lpc_acpi_name(const struct device *dev) @@ -743,10 +731,8 @@
/* Call SMM finalize() handlers before resume */ if (CONFIG(HAVE_SMI_HANDLER)) { - if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || - acpi_is_wakeup_s3()) { + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) outb(APM_CNT_FINALIZE, APM_CNT); - } } }
@@ -777,7 +763,7 @@ };
static const struct pci_driver pch_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c index 1baa7df..4637d3b 100644 --- a/src/southbridge/intel/ibexpeak/madt.c +++ b/src/southbridge/intel/ibexpeak/madt.c @@ -25,32 +25,27 @@ current = acpi_create_madt_lapics(current);
/* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 1, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 1, IO_APIC_ADDR, 0);
/* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, MP_IRQ_POLARITY_DEFAULT | MP_IRQ_TRIGGER_DEFAULT); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_LEVEL); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, + MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
/* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 2, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 3, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) current, 0, + MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE, 0x01); + + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) current, 1, + MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE, 0x01); + + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) current, 2, + MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE, 0x01); + + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) current, 3, + MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE, 0x01); return current; } diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h index 2864c51..75b6596 100644 --- a/src/southbridge/intel/ibexpeak/me.h +++ b/src/southbridge/intel/ibexpeak/me.h @@ -23,7 +23,7 @@ * Management Engine PCI registers */
-#define PCI_CPU_DEVICE PCI_DEV(0,0,0) +#define PCI_CPU_DEVICE PCI_DEV(0, 0, 0) #define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */
diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 85d858b..a1f1cce 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -144,6 +144,7 @@ /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; } __packed global_nvs_t; + check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
/* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c index 1b9f515..dc3435d 100644 --- a/src/southbridge/intel/ibexpeak/pch.c +++ b/src/southbridge/intel/ibexpeak/pch.c @@ -85,8 +85,7 @@
/* Ensure memory, io, and bus master are all disabled */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(dev, PCI_COMMAND, reg32);
/* Disable this device if possible */ diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 555b5ca..5bcdf89 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -40,12 +40,13 @@ pci_write_config32(dev, SATA_SIRD, value); }
+#define IDE_TIM_PARAMETERS (IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS) static void sata_init(struct device *dev) { u32 reg32; u16 reg16; /* Get the chip configuration */ - config_t *config = dev->chip_info; + const config_t *config = dev->chip_info; u8 sata_mode;
printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -75,10 +76,9 @@ pci_write_config8(dev, INTR_LN, 0x0b);
/* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); + pci_write_config16(dev, IDE_TIM_PRI, IDE_TIM_PARAMETERS); + + pci_write_config16(dev, IDE_TIM_SEC, IDE_TIM_PARAMETERS);
/* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, 0); @@ -96,9 +96,8 @@
/* SATA Initialization register */ pci_write_config32(dev, 0x94, - ((config-> - sata_port_map ^ 0x3f) << 24) | 0x183 | - 0x40000000); + ((config->sata_port_map ^ 0x3f) << 24) | 0x183 | 0x40000000); + pci_write_config32(dev, 0x98, 0x00590200);
/* Initialize AHCI memory-mapped space */ @@ -106,13 +105,12 @@ printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS + reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS /* Set ISS, if available */ if (config->sata_interface_speed_support) { reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) - << 20; + reg32 |= (config->sata_interface_speed_support & 0x03) << 20; } write32(abar + 0x00, reg32); /* PI (Ports implemented) */ @@ -139,9 +137,7 @@ reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16);
- /* Native mode capable on both primary and secondary (0xa) - * or'ed with enabled (0x50) = 0xf - */ + /* Native mode capable on both primary and secondary or'ed with enabled */ pci_write_config8(dev, 0x09, 0x8f);
/* Set Interrupt Line */ @@ -149,10 +145,8 @@ pci_write_config8(dev, INTR_LN, 0xff);
/* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); + pci_write_config16(dev, IDE_TIM_PRI, IDE_TIM_PARAMETERS); + pci_write_config16(dev, IDE_TIM_SEC, IDE_TIM_PARAMETERS);
/* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, 0); @@ -169,9 +163,7 @@ pci_write_config16(dev, 0x92, reg16);
/* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config-> - sata_port_map ^ 0x3f) << 24) | 0x183); + pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); }
/* Additional Programming Requirements */ @@ -198,6 +190,7 @@ sir_write(dev, 0xc8, 0x0c0c0c0c); sir_write(dev, 0xd4, 0x10000000); } +#undef IDE_TIM_PARAMETERS
static void sata_enable(struct device *dev) { @@ -235,25 +228,25 @@ };
static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .enable = sata_enable, - .acpi_fill_ssdt = sata_fill_ssdt, - .scan_bus = 0, - .ops_pci = &sata_pci_ops, + .init = sata_init, + .enable = sata_enable, + .acpi_fill_ssdt = sata_fill_ssdt, + .scan_bus = NULL, + .ops_pci = &sata_pci_ops, };
static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_1, PCI_DID_INTEL_IBEXPEAK_MOBILE_SATA_AHCI, PCI_DID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_2, - 0 + 0, };
static const struct pci_driver pch_sata __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index b06b1cd..46bf6e9 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -29,7 +29,7 @@
/* Enable clock gating */ reg16 = pci_read_config32(dev, 0x80); - reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); + reg16 &= ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)); pci_write_config32(dev, 0x80, reg16);
/* Set Receive Slave Address */ @@ -65,12 +65,12 @@ }
static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, };
static struct pci_operations smbus_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static void smbus_read_resources(struct device *dev) @@ -87,20 +87,20 @@ }
static struct device_operations smbus_ops = { - .read_resources = smbus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_smbus, - .init = pch_smbus_init, - .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &smbus_pci_ops, + .read_resources = smbus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_smbus, + .init = pch_smbus_init, + .ops_smbus_bus = &lops_smbus_bus, + .ops_pci = &smbus_pci_ops, };
static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, PCI_DID_INTEL_IBEXPEAK_SMBUS, - 0 + 0, };
static const struct pci_driver pch_smbus __pci_driver = { diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 937078d..2f44bc8 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -29,18 +29,18 @@
#include "nvs.h"
-/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind +/* + * We are using PCIe accesses for now + * 1. the chipset can do it + * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ #include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmutil.h>
-/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located - * by coreboot. - */ +/* GNVS needs to be updated by an 0xea PM Trap (B2) after it has been located by coreboot. */ static global_nvs_t *gnvs; + global_nvs_t *smm_get_gnvs(void) { return gnvs; @@ -51,9 +51,10 @@ switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: - * On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 + /* + * gnvs->smif: + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 */ gnvs->smif = 0; return 1; /* IO trap handled */ @@ -63,8 +64,7 @@ return 0; }
-static void southbridge_gate_memory_reset_real(int offset, - u16 use, u16 io, u16 lvl) +static void southbridge_gate_memory_reset_real(int offset, u16 use, u16 io, u16 lvl) { u32 reg32;
@@ -125,7 +125,7 @@ RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { + for (i = 16; i < 20; i++) { if (trap_cycle & (1 << i)) mask |= (0xff << ((i - 16) << 2)); } @@ -135,11 +135,12 @@ if (IOTRAP(3)) { if (gnvs && gnvs->smif) io_trap_handler(gnvs->smif); // call function smif + return; }
- /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ + /* IOTRAP(2) currently unused */ + /* IOTRAP(1) currently unused */
/* IOTRAP(0) SMIC */ if (IOTRAP(0)) { @@ -147,15 +148,15 @@ printk(BIOS_DEBUG, "SMI1 command\n"); data = RCBA32(0x1e18); data &= mask; - // if (smi1) - // southbridge_smi_command(data); - // return; } // Fall through to debug }
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i = 0; i < 4; i++) + if (IOTRAP(i)) + printk(BIOS_DEBUG, " TRAP = %d\n", i); + printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); @@ -170,8 +171,8 @@
void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); + const em64t101_smm_state_save_area_t *state = smi_apmc_find_state_save(apm_cnt); + if (state) { /* EBX in the state save contains the GNVS pointer */ gnvs = (global_nvs_t *)((u32)state->rbx); diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 2664c65..67060ef 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -48,21 +48,21 @@ };
static struct device_operations thermal_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = thermal_init, - .scan_bus = 0, - .ops_pci = &pci_ops, + .init = thermal_init, + .scan_bus = 0, + .ops_pci = &pci_ops, };
static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_IBEXPEAK_THERMAL, - 0 + 0, };
static const struct pci_driver pch_thermal __pci_driver = { - .ops = &thermal_ops, - .vendor = PCI_VENDOR_ID_INTEL, + .ops = &thermal_ops, + .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index f4b975a..8e80919 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -56,8 +56,7 @@ if (res) { /* Number of ports and companion controllers. */ reg32 = read32((u32 *)(uintptr_t)(res->base + 4)); - write32((u32 *)(uintptr_t)(res->base + 4), - (reg32 & 0xfff00000) | 2); + write32((u32 *)(uintptr_t)(res->base + 4), (reg32 & 0xfff00000) | 2); }
/* Restore protection. */ @@ -66,8 +65,7 @@ printk(BIOS_DEBUG, "done.\n"); }
-static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { u8 access_cntl;
@@ -88,22 +86,22 @@ };
static struct device_operations usb_ehci_ops = { - .read_resources = pci_ehci_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_ehci_init, - .scan_bus = 0, - .ops_pci = &lops_pci, + .read_resources = pci_ehci_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_ehci_init, + .scan_bus = NULL, + .ops_pci = &lops_pci, };
static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_IBEXPEAK_EHCI_1, PCI_DID_INTEL_IBEXPEAK_EHCI_2, - 0 + 0, };
static const struct pci_driver pch_usb_ehci __pci_driver = { - .ops = &usb_ehci_ops, - .vendor = PCI_VENDOR_ID_INTEL, + .ops = &usb_ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, };
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40117 )
Change subject: sb/intel/ibexpeak: Do some cosmetic fixes ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40117/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40117/1//COMMIT_MSG@7 PS1, Line 7: sb/intel/ibexpeak: Do some cosmetic fixes Might provide some more details. Using 'cosmetic fixes' I would not expect code changes
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40117 )
Change subject: sb/intel/ibexpeak: Do some cosmetic fixes ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40117/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40117/1//COMMIT_MSG@7 PS1, Line 7: sb/intel/ibexpeak: Do some cosmetic fixes
Might provide some more details. […]
When I say "cosmetic", it is because the resulting binary does not change at all. But yes, I can add a summary of the changes I have done.
(sure, I may have rototilled the entire southbridge code, but as the binaries are the same, I didn't break anything 😄)
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40117 )
Change subject: sb/intel/ibexpeak: Do some cosmetic fixes ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/40117/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40117/1//COMMIT_MSG@7 PS1, Line 7: sb/intel/ibexpeak: Do some cosmetic fixes
When I say "cosmetic", it is because the resulting binary does not change at all. […]
Agree.
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40117 )
Change subject: sb/intel/ibexpeak: Do some cosmetic fixes ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Frans Hendriks (Code Review)