Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85834?usp=email )
Change subject: superio/nuvoton: Add NCT5535D ......................................................................
superio/nuvoton: Add NCT5535D
NCT5535D is a 64-pin LPC super I/O chip found on many Asus P8x7x series mainboards with no publicly available datasheet. However, based on mb/asus/p8z77-v_lx2, this chip can probably be driven like a NCT6779D, on which this is based.
Devices not present on this chip compared to NCT6779D are parallel port, serial port B, GPIOs 0,1,3,6.
p8z77-v_lx2 still builds once modified for this chip, but is not tested further.
Change-Id: I3fe0dd6fc3010a50b781ca7c5c39ea73b91978a5 Signed-off-by: Keith Hui buurin@gmail.com --- A src/superio/nuvoton/nct5535d/Kconfig A src/superio/nuvoton/nct5535d/Makefile.mk A src/superio/nuvoton/nct5535d/acpi/superio.asl A src/superio/nuvoton/nct5535d/nct5535d.h A src/superio/nuvoton/nct5535d/superio.c 5 files changed, 304 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85834/1
diff --git a/src/superio/nuvoton/nct5535d/Kconfig b/src/superio/nuvoton/nct5535d/Kconfig new file mode 100644 index 0000000..3dc2286 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/Kconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SUPERIO_NUVOTON_NCT5535D + bool + select SUPERIO_NUVOTON_COMMON_PRE_RAM + select HAVE_POWER_STATE_AFTER_FAILURE diff --git a/src/superio/nuvoton/nct5535d/Makefile.mk b/src/superio/nuvoton/nct5535d/Makefile.mk new file mode 100644 index 0000000..1b48a19 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/Makefile.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5535D) += superio.c diff --git a/src/superio/nuvoton/nct5535d/acpi/superio.asl b/src/superio/nuvoton/nct5535d/acpi/superio.asl new file mode 100644 index 0000000..8da1f01 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/acpi/superio.asl @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the NCT5535D SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x2 SP1 Implemented, untested + * 0x5 KBC Implemented, untested + * 0x8 GPIO Implemented, untested + * 0xb HWM Implemented, untested + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * NCT5535D_SHOW_SP1 If defined, Serial Port 1 will be exposed. + * NCT5535D_SHOW_KBC If defined, the Keyboard Controller will be exposed. + * NCT5535D_SHOW_GPIO If defined, GPIO support will be exposed. + * NCT5535D_SHOW_HWM If defined, the Environment Controller will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME NCT5535D +#include <superio/acpi/pnp.asl> + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +#define ENABLE_KEYBOARD_WAKEUP SKWK +#define POWER_LOSS_CONTROL SPWL + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Nuvoton NCT5535D Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8, + } + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + ACT1, 1, /* Logical device activation */ + ACT2, 1, /* Logical device activation */ + ACT3, 1, /* Logical device activation */ + ACT4, 1, /* Logical device activation */ + ACT5, 1, /* Logical device activation */ + ACT6, 1, /* Logical device activation */ + ACT7, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + Offset (0x64), + PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ + PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + Offset (0x72), + PNP_IRQ1, 8, /* Second IRQ */ + Offset (0x74), + PNP_DMA0, 8, /* DRQ */ + Offset (0xe0), /* Config register 0xe0 etc. */ + ,6, + ENABLE_KEYBOARD_WAKEUP, 1, + Offset (0xe4), + ,5, + POWER_LOSS_CONTROL, 2, + } + + Method (_CRS) + { + /* Announce the used I/O ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + Method (SIOS, 1, NotSerialized) + { + if (Arg0 == 5) + { + } + Else + { + } + } + + Method (SIOW, 1, NotSerialized) + { + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include <superio/acpi/pnp_config.asl> + +#ifdef NCT5535D_SHOW_SP1 + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef NCT5535D_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 + #define SUPERIO_KBC_PS2M + #include <superio/acpi/pnp_kbc.asl> +#endif + +#ifdef NCT5535D_SHOW_HWM + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_LDN 11 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IO1 0x08, 0x08 + #define SUPERIO_PNP_IRQ0 + #include <superio/acpi/pnp_generic.asl> +#endif + +#ifdef NCT5535D_SHOW_GPIO + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #undef PNP_DEVICE_ACTIVE + #define PNP_DEVICE_ACTIVE ACT3 + #define SUPERIO_PNP_LDN 8 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #include <superio/acpi/pnp_generic.asl> +#endif +} diff --git a/src/superio/nuvoton/nct5535d/nct5535d.h b/src/superio/nuvoton/nct5535d/nct5535d.h new file mode 100644 index 0000000..9dbbee4 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/nct5535d.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_NUVOTON_NCT5535D_H +#define SUPERIO_NUVOTON_NCT5535D_H + +/* Logical Device Numbers (LDN). */ +#define NCT5535D_SP1 0x02 /* UART */ +#define NCT5535D_KBC 0x05 /* PS/2 keyboard and mouse */ +#define NCT5535D_CIR 0x06 /* Consumer IR */ +#define NCT5535D_GPIO678_V 0x07 /* GPIO 6/7/8 */ +#define NCT5535D_WDT1_GPIO01_V 0x08 /* WDT1, GPIO 0/1 */ +#define NCT5535D_GPIO12345678_V 0x09 /* GPIO 2/5/8 */ +#define NCT5535D_ACPI 0x0A /* ACPI */ +#define NCT5535D_HWM_FPLED 0x0B /* Hardware monitor & front LED */ +#define NCT5535D_WDT1 0x0D /* Watchdog timer 1 */ +#define NCT5535D_CIRWKUP 0x0E /* CIR wakeup */ +#define NCT5535D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */ +#define NCT5535D_PRT80 0x14 /* Port 80 UART */ +#define NCT5535D_DSLP 0x16 /* Deep sleep */ + +/* virtual LDN for GPIO */ + +#define NCT5535D_GPIOBASE ((3 << 8) | NCT5535D_WDT1_GPIO01_V) + +#define NCT5535D_GPIO2 ((2 << 8) | NCT5535D_GPIO12345678_V) +#define NCT5535D_GPIO4 ((4 << 8) | NCT5535D_GPIO12345678_V) +#define NCT5535D_GPIO5 ((5 << 8) | NCT5535D_GPIO12345678_V) +#define NCT5535D_GPIO7 ((7 << 8) | NCT5535D_GPIO12345678_V) +#define NCT5535D_GPIO8 ((0 << 8) | NCT5535D_GPIO12345678_V) + +#endif /* SUPERIO_NUVOTON_NCT5535D_H */ diff --git a/src/superio/nuvoton/nct5535d/superio.c b/src/superio/nuvoton/nct5535d/superio.c new file mode 100644 index 0000000..5532353 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/superio.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <option.h> +#include <superio/conf_mode.h> + +#include "nct5535d.h" + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +static void nct5535d_init(struct device *dev) +{ + uint8_t byte; + uint8_t power_status; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM etc. */ + case NCT5535D_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + case NCT5535D_ACPI: + /* Set power state after power fail */ + power_status = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + byte = pnp_read_config(dev, 0xe4); + byte &= ~0x04; + if (power_status == MAINBOARD_POWER_ON) + byte |= (0x1 << 5); + else if (power_status == MAINBOARD_POWER_KEEP) + byte |= (0x2 << 5); + pnp_write_config(dev, 0xe4, byte); + pnp_exit_conf_mode(dev); + printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off"); + break; + } +} + +static struct device_operations ops = { + .read_resources = noop_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct5535d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, NCT5535D_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, NCT5535D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + 0x0fff, 0x0fff, }, + { NULL, NCT5535D_ACPI}, + { NULL, NCT5535D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + 0x0ffe, 0x0ffe, }, + { NULL, NCT5535D_GPIO678_V}, + { NULL, NCT5535D_WDT1}, + { NULL, NCT5535D_GPIO_PP_OD}, + { NULL, NCT5535D_PRT80}, + { NULL, NCT5535D_DSLP}, + { NULL, NCT5535D_GPIOBASE, PNP_IO0, 0x0ff8, }, + { NULL, NCT5535D_GPIO2}, + { NULL, NCT5535D_GPIO4}, + { NULL, NCT5535D_GPIO5}, + { NULL, NCT5535D_GPIO7}, + { NULL, NCT5535D_GPIO8}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct5535d_ops = { + .name = "NUVOTON NCT5535D Super I/O", + .enable_dev = enable_dev, +};
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Keith Hui (Code Review)