Change in ...coreboot[master]: [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33549

Change subject: [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

[RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

Most mainboards do nothing but setting up a similar decode range so
move it to a common place. All IO ports below 0x1000 are allocated to
the LPC device by default so this should not be an issue.

Lynxpoint does this too.

TODO remove most mainboard specific setups.

Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans 
---
M src/southbridge/intel/bd82x6x/early_pch.c
1 file changed, 12 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/33549/1

diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 0082c91..ef3ee77 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -258,8 +258,16 @@
    write_pmbase16(TCO1_CNT, 1 << 11);	/* halt timer */
 }

-static void pch_enable_lpc_gen_decode(void)
+static void pch_enable_lpc_decode(void)
 {
+	/* Set COM1/COM2 decode range */
+	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
+
+	/* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */
+	u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN
+		| KBC_LPC_EN | MC_LPC_EN;
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config);
+
    const struct device *dev = pcidev_on_root(0x1f, 0);
    const struct southbridge_intel_bd82x6x_config *config = NULL;

@@ -279,9 +287,10 @@

void early_pch_init(void)
 {
-	pch_enable_lpc();

-	pch_enable_lpc_gen_decode();
+	pch_enable_lpc_decode();
+
+	pch_enable_lpc();

pch_enable_bars();

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33549 )

Change subject: [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/33549/1/src/southbridge/intel/bd82x6x/early_... 
File src/southbridge/intel/bd82x6x/early_pch.c:

https://review.coreboot.org/#/c/33549/1/src/southbridge/intel/bd82x6x/early_... 
PS1, Line 293: pch_enable_lpc();
one option is to get rid of this an provide an option in the devicetree to override the default decode ranges if needed.

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33549 )

Change subject: [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

Patch Set 1: Code-Review+1

What if a mainboard requires a different decode range?

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33549 )

Change subject: [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

Patch Set 1:
> Patch Set 1: Code-Review+1
>
> What if a mainboard requires a different decode range?

The idea is to either have a function to override it or have an option to override it from the devicetree. Another option is to simply enable all decode ranges.

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33549 )

Change subject: [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

Patch Set 2: Code-Review+1

Should be done on all southbridge intel platforms.
See comments in 33548.

Change in coreboot[master]: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

[Arthur Heymans (Code Review)]

Hello Angel Pons, Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33549

to look at the new patch set (#3).

Change subject: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

This sets up some common default LPC decode ranges in a common place.
This may set up more decode ranges than needed but that typically does
not hurt. Mainboards needing additional ranges can do so in the
mainboard pch_enable_lpc hook.

Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans 
---
M src/mainboard/asrock/b75pro3-m/romstage.c
M src/mainboard/asus/h61m-cs/romstage.c
M src/mainboard/asus/maximus_iv_gene-z/romstage.c
M src/mainboard/compulab/intense_pc/romstage.c
M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/romstage.c
M src/mainboard/hp/2570p/romstage.c
M src/mainboard/hp/2760p/romstage.c
M src/mainboard/hp/8460p/romstage.c
M src/mainboard/hp/8470p/romstage.c
M src/mainboard/hp/8770w/romstage.c
M src/mainboard/hp/compaq_8200_elite_sff/romstage.c
M src/mainboard/hp/folio_9470m/romstage.c
M src/mainboard/hp/revolve_810_g1/romstage.c
M src/mainboard/hp/z220_sff_workstation/romstage.c
M src/mainboard/intel/dcp847ske/early_southbridge.c
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/lenovo/s230u/romstage.c
M src/mainboard/lenovo/t420/romstage.c
M src/mainboard/lenovo/t420s/romstage.c
M src/mainboard/lenovo/t430/romstage.c
M src/mainboard/lenovo/t430s/romstage.c
M src/mainboard/lenovo/t520/romstage.c
M src/mainboard/lenovo/t530/romstage.c
M src/mainboard/lenovo/x131e/romstage.c
M src/mainboard/lenovo/x1_carbon_gen1/romstage.c
M src/mainboard/lenovo/x220/romstage.c
M src/mainboard/lenovo/x230/romstage.c
M src/mainboard/msi/ms7707/romstage.c
M src/mainboard/roda/rv11/variants/rv11/romstage.c
M src/mainboard/roda/rv11/variants/rw11/romstage.c
M src/mainboard/sapphire/pureplatinumh61/romstage.c
M src/southbridge/intel/bd82x6x/early_pch.c
35 files changed, 12 insertions(+), 153 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/33549/3

Change in coreboot[master]: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

[Arthur Heymans (Code Review)]

Hello Alexander Couzens, Patrick Rudolph, Angel Pons, Patrick Rudolph, Tristan Corrick, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33549

to look at the new patch set (#4).

Change subject: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

This sets up some common default LPC decode ranges in a common place.
This may set up more decode ranges than needed but that typically does
not hurt. Mainboards needing additional ranges can do so in the
mainboard pch_enable_lpc hook.

Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans 
---
M src/mainboard/asrock/b75pro3-m/romstage.c
M src/mainboard/asus/h61m-cs/romstage.c
M src/mainboard/asus/maximus_iv_gene-z/romstage.c
M src/mainboard/compulab/intense_pc/romstage.c
M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/romstage.c
M src/mainboard/hp/2570p/romstage.c
M src/mainboard/hp/2760p/romstage.c
M src/mainboard/hp/8460p/romstage.c
M src/mainboard/hp/8470p/romstage.c
M src/mainboard/hp/8770w/romstage.c
M src/mainboard/hp/compaq_8200_elite_sff/romstage.c
M src/mainboard/hp/folio_9470m/romstage.c
M src/mainboard/hp/revolve_810_g1/romstage.c
M src/mainboard/hp/z220_sff_workstation/romstage.c
M src/mainboard/intel/dcp847ske/early_southbridge.c
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/lenovo/s230u/romstage.c
M src/mainboard/lenovo/t420/romstage.c
M src/mainboard/lenovo/t420s/romstage.c
M src/mainboard/lenovo/t430/romstage.c
M src/mainboard/lenovo/t430s/romstage.c
M src/mainboard/lenovo/t520/romstage.c
M src/mainboard/lenovo/t530/romstage.c
M src/mainboard/lenovo/x131e/romstage.c
M src/mainboard/lenovo/x1_carbon_gen1/romstage.c
M src/mainboard/lenovo/x220/romstage.c
M src/mainboard/lenovo/x230/romstage.c
M src/mainboard/msi/ms7707/romstage.c
M src/mainboard/roda/rv11/variants/rv11/romstage.c
M src/mainboard/roda/rv11/variants/rw11/romstage.c
M src/mainboard/sapphire/pureplatinumh61/romstage.c
M src/southbridge/intel/bd82x6x/early_pch.c
35 files changed, 12 insertions(+), 138 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/33549/4

Change in coreboot[master]: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33549 )

Change subject: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

Patch Set 4: Code-Review+2

Would be nice to have non default decode ranges in devicetree.

Change in coreboot[master]: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33549 )

Change subject: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/33549/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/33549/4//COMMIT_MSG@7 
PS4, Line 7: Setup
Set up

Change in coreboot[master]: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33549 )

Change subject: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

Patch Set 4: Code-Review-1

(6 comments)

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/asrock/b75pro... 
File src/mainboard/asrock/b75pro3-m/romstage.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/asrock/b75pro... 
PS4, Line 29: LPT_LPC_EN
this decode is missing in the common code

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/google/link/r... 
File src/mainboard/google/link/romstage.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/google/link/r... 
PS4, Line 39: GAMEL_LPC_EN
is this really used? if not, this can also be dropped

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/intel/dcp847s... 
File src/mainboard/intel/dcp847ske/early_southbridge.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/intel/dcp847s... 
PS4, Line 41: 	pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);
this line shouldn't be dropped

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/intel/emerald... 
File src/mainboard/intel/emeraldlake2/romstage.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/intel/emerald... 
PS4, Line 33: pci_devfn_t dev = PCH_LPC_DEV;
            : 
            : 	/* Enable SuperIO + PS/2 Keyboard/Mouse */
            : 	u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN;
            : 	pci_write_config16(dev, LPC_EN, lpc_config);
            : 
            : 	/* Enable COM1 */
            : 	if (sio1007_enable_uart_at(SIO_PORT)) {
            : 		pci_write_config16(dev, LPC_EN,
            : 				   lpc_config | COMA_LPC_EN);
this can be dropped

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/roda/rv11/var... 
File src/mainboard/roda/rv11/variants/rw11/romstage.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/roda/rv11/var... 
PS4, Line 35: COMB_LPC_EN
if we always enable com B, this could also be dropped

https://review.coreboot.org/c/coreboot/+/33549/4/src/southbridge/intel/bd82x... 
File src/southbridge/intel/bd82x6x/early_pch.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/southbridge/intel/bd82x... 
PS4, Line 264: 		| KBC_LPC_EN | MC_LPC_EN;
| LPT_LPC_EN and | COMB_LPC_EN ?

Change in coreboot[master]: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33549 )

Change subject: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

Patch Set 4:

I like where the patch is heading; on i think 2 board it possibly breaks some things

Change in coreboot[master]: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33549 )

Change subject: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

Patch Set 4:

(6 comments)

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/asrock/b75pro... 
File src/mainboard/asrock/b75pro3-m/romstage.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/asrock/b75pro... 
PS4, Line 29: LPT_LPC_EN
> this decode is missing in the common code

Hmm missed that. Thx

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/google/link/r... 
File src/mainboard/google/link/romstage.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/google/link/r... 
PS4, Line 39: GAMEL_LPC_EN
> is this really used? if not, this can also be dropped

I can do that in a followup patch.

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/intel/dcp847s... 
File src/mainboard/intel/dcp847ske/early_southbridge.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/intel/dcp847s... 
PS4, Line 41: 	pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);
> this line shouldn't be dropped

yes, this is done via the devicetree now.

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/intel/emerald... 
File src/mainboard/intel/emeraldlake2/romstage.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/intel/emerald... 
PS4, Line 33: pci_devfn_t dev = PCH_LPC_DEV;
            : 
            : 	/* Enable SuperIO + PS/2 Keyboard/Mouse */
            : 	u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN;
            : 	pci_write_config16(dev, LPC_EN, lpc_config);
            : 
            : 	/* Enable COM1 */
            : 	if (sio1007_enable_uart_at(SIO_PORT)) {
            : 		pci_write_config16(dev, LPC_EN,
            : 				   lpc_config | COMA_LPC_EN);
> this can be dropped

sio1007_enable_uart_at(SIO_PORT) still needs to be called I think. I think the intention is to not set up COMA decoding if that failed to somehow avoid a slow boot?

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/roda/rv11/var... 
File src/mainboard/roda/rv11/variants/rw11/romstage.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/roda/rv11/var... 
PS4, Line 35: COMB_LPC_EN
> if we always enable com B, this could also be dropped

I don't mind doing that.

https://review.coreboot.org/c/coreboot/+/33549/4/src/southbridge/intel/bd82x... 
File src/southbridge/intel/bd82x6x/early_pch.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/southbridge/intel/bd82x... 
PS4, Line 264: 		| KBC_LPC_EN | MC_LPC_EN;
> | LPT_LPC_EN and | COMB_LPC_EN ?

fine by me

Change in coreboot[master]: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33549 )

Change subject: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/intel/dcp847s... 
File src/mainboard/intel/dcp847ske/early_southbridge.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/intel/dcp847s... 
PS4, Line 41: 	pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);
> > this line shouldn't be dropped […]

ok

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/intel/emerald... 
File src/mainboard/intel/emeraldlake2/romstage.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/intel/emerald... 
PS4, Line 33: pci_devfn_t dev = PCH_LPC_DEV;
            : 
            : 	/* Enable SuperIO + PS/2 Keyboard/Mouse */
            : 	u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN;
            : 	pci_write_config16(dev, LPC_EN, lpc_config);
            : 
            : 	/* Enable COM1 */
            : 	if (sio1007_enable_uart_at(SIO_PORT)) {
            : 		pci_write_config16(dev, LPC_EN,
            : 				   lpc_config | COMA_LPC_EN);
> > this can be dropped […]

hm, might be. keep this for now then

Change in coreboot[master]: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

[Arthur Heymans (Code Review)]

Hello Alexander Couzens, Patrick Rudolph, Felix Held, Angel Pons, Patrick Rudolph, Tristan Corrick, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33549

to look at the new patch set (#5).

Change subject: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

This sets up some common default LPC decode ranges in a common place.
This may set up more decode ranges than needed but that typically does
not hurt. Mainboards needing additional ranges can do so in the
mainboard pch_enable_lpc hook.

Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans 
---
M src/mainboard/asrock/b75pro3-m/romstage.c
M src/mainboard/asus/h61m-cs/romstage.c
M src/mainboard/asus/maximus_iv_gene-z/romstage.c
M src/mainboard/asus/p8z77-m_pro/romstage.c
M src/mainboard/compulab/intense_pc/romstage.c
M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/romstage.c
M src/mainboard/hp/2570p/romstage.c
M src/mainboard/hp/2760p/romstage.c
M src/mainboard/hp/8460p/romstage.c
M src/mainboard/hp/8470p/romstage.c
M src/mainboard/hp/8770w/romstage.c
M src/mainboard/hp/compaq_8200_elite_sff/romstage.c
M src/mainboard/hp/folio_9470m/romstage.c
M src/mainboard/hp/revolve_810_g1/romstage.c
M src/mainboard/hp/z220_sff_workstation/romstage.c
M src/mainboard/intel/dcp847ske/early_southbridge.c
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/lenovo/l520/romstage.c
M src/mainboard/lenovo/s230u/romstage.c
M src/mainboard/lenovo/t420/romstage.c
M src/mainboard/lenovo/t420s/romstage.c
M src/mainboard/lenovo/t430/romstage.c
M src/mainboard/lenovo/t430s/romstage.c
M src/mainboard/lenovo/t520/romstage.c
M src/mainboard/lenovo/t530/romstage.c
M src/mainboard/lenovo/x131e/romstage.c
M src/mainboard/lenovo/x1_carbon_gen1/romstage.c
M src/mainboard/lenovo/x220/romstage.c
M src/mainboard/lenovo/x230/romstage.c
M src/mainboard/msi/ms7707/romstage.c
M src/mainboard/roda/rv11/variants/rv11/romstage.c
M src/mainboard/roda/rv11/variants/rw11/romstage.c
M src/mainboard/sapphire/pureplatinumh61/romstage.c
M src/southbridge/intel/bd82x6x/early_pch.c
37 files changed, 18 insertions(+), 193 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/33549/5

Change in coreboot[master]: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33549 )

Change subject: sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
......................................................................

Patch Set 5: Code-Review+2

(2 comments)

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/roda/rv11/var... 
File src/mainboard/roda/rv11/variants/rw11/romstage.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/roda/rv11/var... 
PS4, Line 35: COMB_LPC_EN
> > if we always enable com B, this could also be dropped […]

Done

https://review.coreboot.org/c/coreboot/+/33549/4/src/southbridge/intel/bd82x... 
File src/southbridge/intel/bd82x6x/early_pch.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/southbridge/intel/bd82x... 
PS4, Line 264: 		| KBC_LPC_EN | MC_LPC_EN;
> > | LPT_LPC_EN and | COMB_LPC_EN ? […]

Done

Change in coreboot[master]: sb/intel/bd82x6x/lpc: Set up default LPC decode ranges

[Arthur Heymans (Code Review)]

Hello Alexander Couzens, Patrick Rudolph, Felix Held, Angel Pons, Patrick Rudolph, Tristan Corrick, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33549

to look at the new patch set (#6).

Change subject: sb/intel/bd82x6x/lpc: Set up default LPC decode ranges
......................................................................

sb/intel/bd82x6x/lpc: Set up default LPC decode ranges

This sets up some common default LPC decode ranges in a common place.
This may set up more decode ranges than needed but that typically does
not hurt. Mainboards needing additional ranges can do so in the
mainboard pch_enable_lpc hook.

Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans 
---
M src/mainboard/asrock/b75pro3-m/romstage.c
M src/mainboard/asus/h61m-cs/romstage.c
M src/mainboard/asus/maximus_iv_gene-z/romstage.c
M src/mainboard/asus/p8z77-m_pro/romstage.c
M src/mainboard/compulab/intense_pc/romstage.c
M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/romstage.c
M src/mainboard/hp/2570p/romstage.c
M src/mainboard/hp/2760p/romstage.c
M src/mainboard/hp/8460p/romstage.c
M src/mainboard/hp/8470p/romstage.c
M src/mainboard/hp/8770w/romstage.c
M src/mainboard/hp/compaq_8200_elite_sff/romstage.c
M src/mainboard/hp/folio_9470m/romstage.c
M src/mainboard/hp/revolve_810_g1/romstage.c
M src/mainboard/hp/z220_sff_workstation/romstage.c
M src/mainboard/intel/dcp847ske/early_southbridge.c
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/lenovo/l520/romstage.c
M src/mainboard/lenovo/s230u/romstage.c
M src/mainboard/lenovo/t420/romstage.c
M src/mainboard/lenovo/t420s/romstage.c
M src/mainboard/lenovo/t430/romstage.c
M src/mainboard/lenovo/t430s/romstage.c
M src/mainboard/lenovo/t520/romstage.c
M src/mainboard/lenovo/t530/romstage.c
M src/mainboard/lenovo/x131e/romstage.c
M src/mainboard/lenovo/x1_carbon_gen1/romstage.c
M src/mainboard/lenovo/x220/romstage.c
M src/mainboard/lenovo/x230/romstage.c
M src/mainboard/msi/ms7707/romstage.c
M src/mainboard/roda/rv11/variants/rv11/romstage.c
M src/mainboard/roda/rv11/variants/rw11/romstage.c
M src/mainboard/sapphire/pureplatinumh61/romstage.c
M src/southbridge/intel/bd82x6x/early_pch.c
37 files changed, 18 insertions(+), 193 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/33549/6

Change in coreboot[master]: sb/intel/bd82x6x/lpc: Set up default LPC decode ranges

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33549 )

Change subject: sb/intel/bd82x6x/lpc: Set up default LPC decode ranges
......................................................................

Patch Set 5:

(4 comments)

https://review.coreboot.org/c/coreboot/+/33549/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/33549/4//COMMIT_MSG@7 
PS4, Line 7: Setup
> Set up

Done

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/asrock/b75pro... 
File src/mainboard/asrock/b75pro3-m/romstage.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/asrock/b75pro... 
PS4, Line 29: LPT_LPC_EN
> > this decode is missing in the common code […]

Done

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/google/link/r... 
File src/mainboard/google/link/romstage.c:

https://review.coreboot.org/c/coreboot/+/33549/4/src/mainboard/google/link/r... 
PS4, Line 39: GAMEL_LPC_EN
> > is this really used? if not, this can also be dropped […]

Ack

https://review.coreboot.org/c/coreboot/+/33549/1/src/southbridge/intel/bd82x... 
File src/southbridge/intel/bd82x6x/early_pch.c:

https://review.coreboot.org/c/coreboot/+/33549/1/src/southbridge/intel/bd82x... 
PS1, Line 293: pch_enable_lpc();
> one option is to get rid of this an provide an option in the devicetree to override the default deco […]

Ack

Change in coreboot[master]: sb/intel/bd82x6x/lpc: Set up default LPC decode ranges

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/33549 )

Change subject: sb/intel/bd82x6x/lpc: Set up default LPC decode ranges
......................................................................

sb/intel/bd82x6x/lpc: Set up default LPC decode ranges

This sets up some common default LPC decode ranges in a common place.
This may set up more decode ranges than needed but that typically does
not hurt. Mainboards needing additional ranges can do so in the
mainboard pch_enable_lpc hook.

Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33549
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
---
M src/mainboard/asrock/b75pro3-m/romstage.c
M src/mainboard/asus/h61m-cs/romstage.c
M src/mainboard/asus/maximus_iv_gene-z/romstage.c
M src/mainboard/asus/p8z77-m_pro/romstage.c
M src/mainboard/compulab/intense_pc/romstage.c
M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/romstage.c
M src/mainboard/hp/2570p/romstage.c
M src/mainboard/hp/2760p/romstage.c
M src/mainboard/hp/8460p/romstage.c
M src/mainboard/hp/8470p/romstage.c
M src/mainboard/hp/8770w/romstage.c
M src/mainboard/hp/compaq_8200_elite_sff/romstage.c
M src/mainboard/hp/folio_9470m/romstage.c
M src/mainboard/hp/revolve_810_g1/romstage.c
M src/mainboard/hp/z220_sff_workstation/romstage.c
M src/mainboard/intel/dcp847ske/early_southbridge.c
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/lenovo/l520/romstage.c
M src/mainboard/lenovo/s230u/romstage.c
M src/mainboard/lenovo/t420/romstage.c
M src/mainboard/lenovo/t420s/romstage.c
M src/mainboard/lenovo/t430/romstage.c
M src/mainboard/lenovo/t430s/romstage.c
M src/mainboard/lenovo/t520/romstage.c
M src/mainboard/lenovo/t530/romstage.c
M src/mainboard/lenovo/x131e/romstage.c
M src/mainboard/lenovo/x1_carbon_gen1/romstage.c
M src/mainboard/lenovo/x220/romstage.c
M src/mainboard/lenovo/x230/romstage.c
M src/mainboard/msi/ms7707/romstage.c
M src/mainboard/roda/rv11/variants/rv11/romstage.c
M src/mainboard/roda/rv11/variants/rw11/romstage.c
M src/mainboard/sapphire/pureplatinumh61/romstage.c
M src/southbridge/intel/bd82x6x/early_pch.c
37 files changed, 18 insertions(+), 193 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved

diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c
index cbd26a5..da895b3 100644
--- a/src/mainboard/asrock/b75pro3-m/romstage.c
+++ b/src/mainboard/asrock/b75pro3-m/romstage.c
@@ -25,9 +25,6 @@

void pch_enable_lpc(void)
 {
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
-	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0000);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/romstage.c
index 94f58c1..2064f14 100644
--- a/src/mainboard/asus/h61m-cs/romstage.c
+++ b/src/mainboard/asus/h61m-cs/romstage.c
@@ -29,7 +29,6 @@

void pch_enable_lpc(void)
 {
-	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/romstage.c
index f0506fb..fcf78d2 100644
--- a/src/mainboard/asus/maximus_iv_gene-z/romstage.c
+++ b/src/mainboard/asus/maximus_iv_gene-z/romstage.c
@@ -42,7 +42,6 @@

void pch_enable_lpc(void)
 {
-	pci_or_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/asus/p8z77-m_pro/romstage.c b/src/mainboard/asus/p8z77-m_pro/romstage.c
index b5593ec..9c5e443 100644
--- a/src/mainboard/asus/p8z77-m_pro/romstage.c
+++ b/src/mainboard/asus/p8z77-m_pro/romstage.c
@@ -32,12 +32,6 @@

void pch_enable_lpc(void)
 {
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			   CNF1_LPC_EN | CNF2_LPC_EN |
-			   KBC_LPC_EN | COMB_LPC_EN);
-
-	/* Set COMB/COM2 IO range to 2F8h-2FFh */
-	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c
index 74f00c2..f74e94d 100644
--- a/src/mainboard/compulab/intense_pc/romstage.c
+++ b/src/mainboard/compulab/intense_pc/romstage.c
@@ -26,9 +26,6 @@
 {
    pci_devfn_t dev = PCH_LPC_DEV;

-	/* Set COM1/COM2 decode range */
-	pci_write_config16(dev, LPC_IO_DEC, 0x0010);
-
    /* Enable SuperIO */
    u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN;
    pci_write_config16(dev, LPC_EN, lpc_config);
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index b35a8b4..ecbd393 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -27,11 +27,6 @@

void pch_enable_lpc(void)
 {
-	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
-			CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
-
-	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
-
    pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
index a51595f..8a17ac9 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
@@ -25,12 +25,6 @@

void pch_enable_lpc(void)
 {
-	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | CNF1_LPC_EN);
-
-	if (!CONFIG(NO_UART_ON_SUPERIO)) {
-		pci_or_config16(PCH_LPC_DEV, LPC_EN, COMA_LPC_EN);
-		pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
-	}
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 8e8d943..d42572b 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -34,9 +34,6 @@

void pch_enable_lpc(void)
 {
-	/* Set COM1/COM2 decode range */
-	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
-
    /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
    pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \
    		   GAMEL_LPC_EN | COMA_LPC_EN);
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index ac06fbc..210c7fc 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -28,9 +28,6 @@

void pch_enable_lpc(void)
 {
-	/* Parrot EC Decode Range Port60/64, Port62/66 */
-	/* Enable EC, PS/2 Keyboard/Mouse */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c
index 6401909..6ffc340 100644
--- a/src/mainboard/hp/2570p/romstage.c
+++ b/src/mainboard/hp/2570p/romstage.c
@@ -22,12 +22,6 @@

void pch_enable_lpc(void)
 {
-	/*
-	 * CNF2 and CNF1 for Super I/O
-	 * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
-	 */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c
index ba6f956..b448f79 100644
--- a/src/mainboard/hp/2760p/romstage.c
+++ b/src/mainboard/hp/2760p/romstage.c
@@ -21,12 +21,6 @@

void pch_enable_lpc(void)
 {
-	/*
-	 * CNF2 and CNF1 for Super I/O
-	 * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
-	 */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c
index f30c3a8..72a62c9 100644
--- a/src/mainboard/hp/8460p/romstage.c
+++ b/src/mainboard/hp/8460p/romstage.c
@@ -25,15 +25,6 @@

void pch_enable_lpc(void)
 {
-	/*
-	 * CNF2 and CNF1 for Super I/O
-	 * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
-	 * Enable parallel port and serial port
-	 */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
-			LPT_LPC_EN | COMA_LPC_EN);
-	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c
index b1375e8..83f382d 100644
--- a/src/mainboard/hp/8470p/romstage.c
+++ b/src/mainboard/hp/8470p/romstage.c
@@ -24,15 +24,6 @@

void pch_enable_lpc(void)
 {
-	/*
-	 * CNF2 and CNF1 for Super I/O
-	 * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
-	 * Enable parallel port and serial port
-	 */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
-			LPT_LPC_EN | COMA_LPC_EN);
-	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c
index 8956b08..2bd9162 100644
--- a/src/mainboard/hp/8770w/romstage.c
+++ b/src/mainboard/hp/8770w/romstage.c
@@ -25,15 +25,6 @@

void pch_enable_lpc(void)
 {
-	/*
-	 * CNF2 and CNF1 for Super I/O
-	 * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
-	 * Enable parallel port and serial port
-	 */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
-			LPT_LPC_EN | COMA_LPC_EN);
-	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c
index 3c38877..258eac7 100644
--- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c
+++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c
@@ -29,16 +29,6 @@

void pch_enable_lpc(void)
 {
-	/*
-	 * Enable SuperIO, TPM, Keyboard, LPT, COMA
-	 * (COMB can be equip on expansion header)
-	 */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-	    CNF2_LPC_EN |CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN |
-	    COMB_LPC_EN | COMA_LPC_EN);
-
-	/* COMA: 3F8h, COMB: 2F8h */
-	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c
index 8ff7813..061a068 100644
--- a/src/mainboard/hp/folio_9470m/romstage.c
+++ b/src/mainboard/hp/folio_9470m/romstage.c
@@ -23,13 +23,6 @@

void pch_enable_lpc(void)
 {
-	/*
-	 * CNF2 and CNF1 for Super I/O
-	 * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
-	 */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c
index 5f8df63..5c83a91 100644
--- a/src/mainboard/hp/revolve_810_g1/romstage.c
+++ b/src/mainboard/hp/revolve_810_g1/romstage.c
@@ -26,13 +26,6 @@

void pch_enable_lpc(void)
 {
-	/*
-	 * CNF2 and CNF1 for Super I/O
-	 * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
-	 */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/z220_sff_workstation/romstage.c b/src/mainboard/hp/z220_sff_workstation/romstage.c
index 54bfae3..6c139ed 100644
--- a/src/mainboard/hp/z220_sff_workstation/romstage.c
+++ b/src/mainboard/hp/z220_sff_workstation/romstage.c
@@ -29,16 +29,6 @@

void pch_enable_lpc(void)
 {
-	/*
-	 * Enable SuperIO, TPM, Keyboard, LPT, COMA
-	 * (COMB can be equip on expansion header)
-	 */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-	    CNF2_LPC_EN | CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN |
-	    COMB_LPC_EN | COMA_LPC_EN);
-
-	/* COMA: 3F8h, COMB: 2F8h */
-	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index 705ace9..9846295 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -27,18 +27,8 @@
 #include "superio.h"
 #include "thermal.h"

-#if CONFIG(DISABLE_UART_ON_TESTPADS)
-#define DEBUG_UART_EN 0
-#else
-#define DEBUG_UART_EN COMA_LPC_EN
-#endif
-
 void pch_enable_lpc(void)
 {
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
-			CNF2_LPC_EN | DEBUG_UART_EN);
-	/* Decode SuperIO 0x0a00 */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index ee3cec1..d56576e 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -32,9 +32,6 @@
 {
    pci_devfn_t dev = PCH_LPC_DEV;

-	/* Set COM1/COM2 decode range */
-	pci_write_config16(dev, LPC_IO_DEC, 0x0010);
-
    /* Enable SuperIO + PS/2 Keyboard/Mouse */
    u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN;
    pci_write_config16(dev, LPC_EN, lpc_config);
diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c
index 426ac4e..82f6377 100644
--- a/src/mainboard/lenovo/l520/romstage.c
+++ b/src/mainboard/lenovo/l520/romstage.c
@@ -24,11 +24,6 @@

void pch_enable_lpc(void)
 {
-	/* EC Decode Range Port60/64, Port62/66 */
-	/* Enable EC, PS/2 Keyboard/Mouse, LPT */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			   CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
-			   LPT_LPC_EN);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c
index dd8fc17..754c49a 100644
--- a/src/mainboard/lenovo/s230u/romstage.c
+++ b/src/mainboard/lenovo/s230u/romstage.c
@@ -29,7 +29,6 @@

void pch_enable_lpc(void)
 {
-	pci_write_config16(PCH_LPC_DEV, LPC_EN, MC_LPC_EN | KBC_LPC_EN);
    pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);

/* Memory map KB9012 EC registers */
diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c
index ebf5aed..e7851f3 100644
--- a/src/mainboard/lenovo/t420/romstage.c
+++ b/src/mainboard/lenovo/t420/romstage.c
@@ -51,11 +51,6 @@

void pch_enable_lpc(void)
 {
-	/* EC Decode Range Port60/64, Port62/66 */
-	/* Enable EC, PS/2 Keyboard/Mouse */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			   CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-
    pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c
index 49de58d..72cbcad 100644
--- a/src/mainboard/lenovo/t420s/romstage.c
+++ b/src/mainboard/lenovo/t420s/romstage.c
@@ -51,11 +51,6 @@

void pch_enable_lpc(void)
 {
-	/* EC Decode Range Port60/64, Port62/66 */
-	/* Enable EC, PS/2 Keyboard/Mouse */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			   CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-
    pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c
index 1f4b90d..3caa443 100644
--- a/src/mainboard/lenovo/t430/romstage.c
+++ b/src/mainboard/lenovo/t430/romstage.c
@@ -51,10 +51,6 @@

void pch_enable_lpc(void)
 {
-	/* EC Decode Range Port60/64, Port62/66 */
-	/* Enable TPM, EC, PS/2 Keyboard/Mouse */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			   CNF2_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c
index e590bb6..34793d1 100644
--- a/src/mainboard/lenovo/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/romstage.c
@@ -21,11 +21,6 @@

void pch_enable_lpc(void)
 {
-	/* EC Decode Range Port60/64, Port62/66 */
-	/* Enable EC, PS/2 Keyboard/Mouse */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			   CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-
    pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index 5c23b8e..75e331e 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -53,11 +53,6 @@

void pch_enable_lpc(void)
 {
-	/* EC Decode Range Port60/64, Port62/66 */
-	/* Enable EC, PS/2 Keyboard/Mouse */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			   CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-
    pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index 67cf97c..cb17a27 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -53,11 +53,6 @@

void pch_enable_lpc(void)
 {
-	/* EC Decode Range Port60/64, Port62/66 */
-	/* Enable EC, PS/2 Keyboard/Mouse */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			   CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-
    pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c
index 5fc5df6..2a6ee27 100644
--- a/src/mainboard/lenovo/x131e/romstage.c
+++ b/src/mainboard/lenovo/x131e/romstage.c
@@ -22,10 +22,6 @@

void pch_enable_lpc(void)
 {
-	/* EC Decode Range Port60/64, Port62/66 */
-	/* Enable TPM, EC, PS/2 Keyboard/Mouse */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			   CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
 }

void mainboard_rcba_config(void)
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
index f666671..b779c4e 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
@@ -30,11 +30,6 @@

void pch_enable_lpc(void)
 {
-	/* EC Decode Range Port60/64, Port62/66 */
-	/* Enable EC, PS/2 Keyboard/Mouse */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			   CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-
    pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index 9ecb8a3..af92f9b 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -29,11 +29,6 @@

void pch_enable_lpc(void)
 {
-	/* EC Decode Range Port60/64, Port62/66 */
-	/* Enable EC, PS/2 Keyboard/Mouse */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			   CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-
    pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 10cddeb..60016a4 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -26,11 +26,6 @@

void pch_enable_lpc(void)
 {
-	/* EC Decode Range Port60/64, Port62/66 */
-	/* Enable EC, PS/2 Keyboard/Mouse */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			   CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-
    pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/romstage.c
index 30bb545..dc3b79d 100644
--- a/src/mainboard/msi/ms7707/romstage.c
+++ b/src/mainboard/msi/ms7707/romstage.c
@@ -23,11 +23,6 @@

void pch_enable_lpc(void)
 {
-	/* IO Decode Ranges Register */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
-	/* LPC IF Enables Register (CNF2_LPC_EN|KBC_LPC_EN) */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400);
-
    u16 reg16;
    reg16 = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xa4);
    reg16 |= (1 << 13); // WOL Enable Override (WOL_EN_OVRD)
diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c
index 685e942..4491370 100644
--- a/src/mainboard/roda/rv11/variants/rv11/romstage.c
+++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c
@@ -23,10 +23,6 @@

void pch_enable_lpc(void)
 {
-	/* Enable KBC on 0x60/0x64 (KBC),
-		  EC on 0x62/0x66 (MC) */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			   KBC_LPC_EN | MC_LPC_EN);
 }

void mainboard_config_superio(void)
diff --git a/src/mainboard/roda/rv11/variants/rw11/romstage.c b/src/mainboard/roda/rv11/variants/rw11/romstage.c
index 97d9d2b..f355578 100644
--- a/src/mainboard/roda/rv11/variants/rw11/romstage.c
+++ b/src/mainboard/roda/rv11/variants/rw11/romstage.c
@@ -27,14 +27,6 @@

void pch_enable_lpc(void)
 {
-	/* COMA on 0x3f8, COMB on 0x2f8 */
-	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
-	/* Enable KBC on 0x60/0x64 (KBC),
-		  EC on 0x62/0x66 (MC),
-		  SIO on 0x2e/0x2f (CNF1) */
-	pci_write_config16(PCH_LPC_DEV, LPC_EN,
-			   CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
-			   COMB_LPC_EN | COMA_LPC_EN);
 }

void mainboard_config_superio(void)
diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c
index c7d8f0f..ff5bb70 100644
--- a/src/mainboard/sapphire/pureplatinumh61/romstage.c
+++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c
@@ -23,8 +23,6 @@

void pch_enable_lpc(void)
 {
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
    pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
 }

diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 73fce3b..df9fdef 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -254,8 +254,22 @@
    write_pmbase16(TCO1_CNT, 1 << 11);	/* halt timer */
 }

-static void pch_enable_lpc_gen_decode(void)
+static void pch_enable_lpc_decode(void)
 {
+	/*
+	 * Enable some common LPC IO ranges:
+	 * - 0x2e/0x2f, 0x4e/0x4f often SuperIO
+	 * - 0x60/0x64, 0x62/0x66 often KBC/EC
+	 * - 0x3f0-0x3f5/0x3f7 FDD
+	 * - 0x378-0x37f and 0x778-0x77f LPT
+	 * - 0x2f8-0x2ff COMB
+	 * - 0x3f8-0x3ff COMA
+	 */
+	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
+		| MC_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+		| COMB_LPC_EN | COMA_LPC_EN);
+
    const struct device *dev = pcidev_on_root(0x1f, 0);
    const struct southbridge_intel_bd82x6x_config *config = NULL;

@@ -275,9 +289,10 @@

void early_pch_init(void)
 {
-	pch_enable_lpc();

-	pch_enable_lpc_gen_decode();
+	pch_enable_lpc_decode();
+
+	pch_enable_lpc();

pch_enable_bars();