Change in coreboot[master]: soc/amd/cezanne: Force resets to be cold

[Marshall Dawson (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Felix Held.
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52982 )

Change subject: soc/amd/cezanne: Force resets to be cold
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Patch Set 2:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/52982/comment/dc463a9b_f0ec6025 
PS1, Line 10: AGESA has cleared it in
            : FSP-S.
> That's pretty funny. […]

Now I'm not seeing it clear either.

File src/soc/amd/cezanne/reset.c:

https://review.coreboot.org/c/coreboot/+/52982/comment/3a1694f4_db65a65f 
PS1, Line 10: /* TODO: is NCP_ERR still valid?  It appears reserved and always 0xff.  b/184281092 */
> ppr says that's it's still valid; see LEGACYIOx000000F0 (FCH::IO::NCP_ERROR) […]

Ack.  I'd experimented a little with HDT, including before the FSP call, and could never see the register behaving correctly.  We can check whether the PSP writes the register, although I can't think of a legitimate reason it would.