Change in coreboot[master]: soc/amd/cezanne: add ACPI CPPC support for AMD

[Julian Schroeder (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held.
Julian Schroeder has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56188 )

Change subject: soc/amd/cezanne: add ACPI CPPC support for AMD
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Patch Set 4:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/56188/comment/1b84f119_06b319e3 
PS4, Line 9: CollaborativeProcessorPerformanceControl
           : See also: uefi.org/specifications
           : This leverages the existing CPPC support and adds a
           : cppc init for AMD/Cezanne.
           :
> maybe: […]

Done

Patchset:

PS4: 
all change requests done

File src/soc/amd/cezanne/cppc.c:

https://review.coreboot.org/c/coreboot/+/56188/comment/cfc9daca_15f303e3 
PS4, Line 168: int
> unsigned int?

Done

File src/soc/amd/cezanne/include/soc/cppc.h:

PS4:
> i'd put the msr number and bit defines in oc/amd/cezanne/include/soc/msr. […]

Done