Change in coreboot[master]: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Angel Pons, Alexander Couzens, Patrick Rudolph.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52942 )

Change subject: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE
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Patch Set 1:

(1 comment)

File src/cpu/intel/socket_p/Kconfig:

https://review.coreboot.org/c/coreboot/+/52942/comment/8749dfdd_6060fc75 
PS1, Line 16: 	default 0x10000
> Looks like Crestline reference code uses a CodeRegion of 0x20000 and a DataRegion of 0x2000

DCACHE_RAM_SIZE would be the data region. for code, we use the size of the stage.

Hmmm, Arthur actually wrote some nice code about it. Size of the code range
is limited so that we don't use more than 256KiB total: `src/cpu/x86/mtrr/xip_cache.c`

Oh, and `t400/` is the only user of Socket P... romstage and bootblock are about
80KiB together. Don't know about verstage, but I guess the 32KiB extra here won't
hurt. Would be nice to test it on any device, though. I could also do that.