Change in coreboot[master]: soc/intel/alderlake: Add support for FSP CNVi pin muxing

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51110 )

Change subject: soc/intel/alderlake: Add support for FSP CNVi pin muxing
......................................................................

soc/intel/alderlake: Add support for FSP CNVi pin muxing

CNVi can mux both the RF_RESET# and CLKREQ# signals. This adds support
for ADL mainboards to set the muxes.

Signed-off-by: Tim Wawrzynczak 
Change-Id: Idda2da4bddbe1be6c740cba4c44ae31b6a63c2fa
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/51110/1

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 13e77cf..c4f6dab 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -317,6 +317,16 @@
    	ISA_SERIAL_BASE_ADDR_3F8,
    	ISA_SERIAL_BASE_ADDR_2F8,
    } IsaSerialUartBase;
+
+	enum {
+		CNVI_CLKREQ_GPP_A9 = 0x3942E609,
+		CNVI_CLKREQ_GPP_F5 = 0x394CE605,
+	} CnviClkreqPinMux;
+
+	enum {
+		CNVI_RF_RESET_GPP_A8 = 0x2942E408,
+		CNVI_RF_RESET_GPP_F4 = 0x194CE404,
+	} CnviRfResetPinMux;
 };

typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 6e6f1af..0938a1d 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -290,6 +290,12 @@
    params->Cx = 1;
    params->PsOnEnable = 1;

+	if (config->CnviClkreqPinMux)
+		params->CnviClkreqPinMux = config->CnviClkreqPinMux;
+
+	if (config->CnviRfResetPinMux)
+		params->CnviRfResetPinMux = config->CnviRfResetPinMux;
+
    mainboard_silicon_init_params(params);
 }