Change in ...coreboot[master]: mb/intel/{kunimitsu,saddlebrook}: Fix false coverity alarms
Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32742
Change subject: mb/intel/{kunimitsu,saddlebrook}: Fix false coverity alarms ......................................................................
mb/intel/{kunimitsu,saddlebrook}: Fix false coverity alarms
Coverity doesn't like the filling of adjacent arrays with a single memcpy(). The structure of the FSP headers doesn't allow us to loop over them either. In case of Kunimitsu we also can't have a better typed solution because of the FSP1.1/FSP2.0 dual port.
Just replicating the functions per channel is probably the best we can do.
CID=1401341, 1401344
Change-Id: I36a141bc00664ccd29d625ac88e76073086a5074 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/intel/kunimitsu/romstage.c M src/mainboard/intel/kunimitsu/romstage_fsp20.c M src/mainboard/intel/kunimitsu/spd/spd.h M src/mainboard/intel/kunimitsu/spd/spd_util.c M src/mainboard/intel/saddlebrook/romstage.c M src/mainboard/intel/saddlebrook/spd/spd.h M src/mainboard/intel/saddlebrook/spd/spd_util.c 7 files changed, 60 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32742/1
diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index f25f88b..1a474da 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -30,8 +30,10 @@ MEMORY_INIT_UPD *memory_params) { spd_memory_init_params(memory_params); - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data0(&memory_params->DqByteMapCh0); + mainboard_fill_dq_map_data1(&memory_params->DqByteMapCh1); + mainboard_fill_dqs_map_data0(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_data1(&memory_params->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); memory_params->MemorySpdDataLen = SPD_LEN; diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c index ee1ddd5..10992f0 100644 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -26,8 +26,10 @@ FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig;
- mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data0(&mem_cfg->DqByteMapCh0); + mainboard_fill_dq_map_data1(&mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data0(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_data1(&mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index 22d371f..e8b42ee 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -55,8 +55,10 @@ return (gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))); } void spd_memory_init_params(MEMORY_INIT_UPD *memory_params); -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_dq_map_data0(void *dq_map_ptr); +void mainboard_fill_dq_map_data1(void *dq_map_ptr); +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); uintptr_t mainboard_get_spd_data(void); diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index b173628..6dcc92d 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -20,23 +20,33 @@ #include "boardid.h" #include "spd.h"
-void mainboard_fill_dq_map_data(void *dq_map_ptr) +void mainboard_fill_dq_map_data0(void *dq_map_ptr) { /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + const u8 dq_map[12] = { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); }
-void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +void mainboard_fill_dq_map_data1(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[12] = { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr) { /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 6, 5, 4, 7 }, - { 2, 3, 0, 1, 6, 7, 4, 5 } }; + const u8 dqs_map[8] = { 0, 1, 3, 2, 6, 5, 4, 7 }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[8] = { 2, 3, 0, 1, 6, 7, 4, 5 }; memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); }
diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 48d39db..7b2687f 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -63,8 +63,10 @@ * should be set in the FSP flash image and should not need to be * changed. */ - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data0(&memory_params->DqByteMapCh0); + mainboard_fill_dq_map_data1(&memory_params->DqByteMapCh1); + mainboard_fill_dqs_map_data0(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_data1(&memory_params->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget);
diff --git a/src/mainboard/intel/saddlebrook/spd/spd.h b/src/mainboard/intel/saddlebrook/spd/spd.h index a5f1af3..47587ed 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd.h +++ b/src/mainboard/intel/saddlebrook/spd/spd.h @@ -19,8 +19,10 @@
#define RCOMP_TARGET_PARAMS 0x5
-void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_dq_map_data0(void *dq_map_ptr); +void mainboard_fill_dq_map_data1(void *dq_map_ptr); +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c index 5055d9a..7f27c31 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd_util.c +++ b/src/mainboard/intel/saddlebrook/spd/spd_util.c @@ -17,23 +17,33 @@ #include <string.h> #include "spd.h"
-void mainboard_fill_dq_map_data(void *dq_map_ptr) +void mainboard_fill_dq_map_data0(void *dq_map_ptr) { /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + const u8 dq_map[12] = { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); }
-void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +void mainboard_fill_dq_map_data1(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[12] = { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr) { /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 2, 3, 6, 7 } }; + const u8 dqs_map[8] = { 0, 1, 3, 2, 4, 5, 6, 7 }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[8] = { 1, 0, 4, 5, 2, 3, 6, 7 }; memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); }
Nico Huber has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32742 )
Change subject: mb/intel/{kunimitsu,saddlebrook}: Fix false coverity alarms ......................................................................
Abandoned
superseded
-
Nico Huber (Code Review)