Change in coreboot[master]: soc/mediatek/mt8186: Modify internal capid to 0xE0

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62563 )

Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0
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soc/mediatek/mt8186: Modify internal capid to 0xE0

The mainboard may not be able to disable the internal cap, so we want
to set 0xe0 for all boards to minimize the internal cap. And a
mainboard implementation may choose XTAL with higher cload if the
frequency requirement is met, and the total capacitance can be tuned
externally for different boards.

BUG=b:218439447
TEST=set capid to 0xe0.

Signed-off-by: Rex-BC Chen 
Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62563
Reviewed-by: Yu-Ping Wu 
Tested-by: build bot (Jenkins) 
---
M src/soc/mediatek/mt8186/rtc.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved
  Rex-BC Chen: Looks good to me, but someone else must approve

diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c
index 2f78be8..7375bc3 100644
--- a/src/soc/mediatek/mt8186/rtc.c
+++ b/src/soc/mediatek/mt8186/rtc.c
@@ -13,7 +13,7 @@
 #include <soc/pmic_wrap.h>
 #include <timer.h>

-#define MT8186_RTC_DXCO_CAPID 0xC0
+#define MT8186_RTC_DXCO_CAPID 0xE0

/* Initialize RTC setting of using DCXO clock */
 static bool rtc_enable_dcxo(void)

10 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.