Attention is currently required from: Jason Glenesk, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49477 )
Change subject: [WIP] ACPI: Move ChromeOS GNVS ......................................................................
[WIP] ACPI: Move ChromeOS GNVS
Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/braswell/acpi/globalnvs.asl M src/soc/intel/broadwell/pch/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl 10 files changed, 12 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/49477/1
diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 70964921..4df4c01 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -11,7 +11,7 @@
External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -24,7 +24,4 @@ TMPS, 8, // 0x17 - Temperature Sensor ID TCRT, 8, // 0x18 - Critical Threshold TPSV, 8, // 0x19 - Passive Threshold - /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> } diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 8bfc7b2..2033330 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -8,7 +8,7 @@
External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -45,7 +45,4 @@ FW01, 32, // 0x28 - xHCI FW RAM addr, boot RAM FW03, 32, // 0x2c - xHCI FW RAM addr, Instruction RAM EH10, 32, // 0x30 - EHCI BAR - /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> } diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 8b03713..403fc17 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -8,7 +8,7 @@
External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -31,8 +31,4 @@ ELNG, 64, // 0x35 - 0x3C EPC Length A4GB, 64, // 0x3D - 0x44 Base of above 4GB MMIO Resource A4GS, 64, // 0x45 - 0x4C Length of above 4GB MMIO Resource - - /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> } diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index ff80c1e..e93b6e8 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -13,7 +13,7 @@
External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -52,10 +52,6 @@ CMEM, 32, /* 0x30 - CBMEM TOC */ TOLM, 32, /* 0x34 - Top of Low Memory */ CBMC, 32, /* 0x38 - coreboot mem console pointer */ - - /* ChromeOS specific */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> }
#include <soc/intel/baytrail/acpi/device_nvs.asl> diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 65b34c1..1d49881 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -13,7 +13,7 @@
External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -54,10 +54,6 @@ CMEM, 32, /* 0x30 - CBMEM TOC */ TOLM, 32, /* 0x34 - Top of Low Memory */ CBMC, 32, /* 0x38 - coreboot mem console pointer */ - - /* ChromeOS specific */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> }
#include <soc/intel/braswell/acpi/device_nvs.asl> diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl index af22568..05b10a0 100644 --- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl @@ -12,7 +12,8 @@ */
External (NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) + +OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -43,10 +44,6 @@ CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit - - /* ChromeOS specific */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> }
#include <soc/intel/braswell/acpi/device_nvs.asl> diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 1333857..c781dbb 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -13,7 +13,7 @@
External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -36,8 +36,4 @@ UIOR, 8, // 0x2f - UART debug controller init on S3 resume A4GB, 64, // 0x30 - 0x37 Base of above 4GB MMIO Resource A4GS, 64, // 0x38 - 0x3f Length of above 4GB MMIO Resource - - /* ChromeOS specific */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> } diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 913d2cf..afd3d22 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -13,7 +13,7 @@
External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -56,10 +56,6 @@ ELNG, 64, // 0x4C - 0x53 EPC Length A4GB, 64, // 0x54 - 0x5B Base of above 4GB MMIO Resource A4GS, 64, // 0x5C - 0x63 Length of above 4GB MMIO Resource - - /* ChromeOS specific */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> }
/* Set flag to enable USB charging in S3 */ diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 9194f3f..c705674 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -11,7 +11,7 @@ */
External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -111,10 +111,6 @@ Offset (0xf5), TPIQ, 8, // 0xf5 - trackpad IRQ value CBMC, 32, - - /* ChromeOS specific */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> }
/* Set flag to enable USB charging in S3 */ diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index d95d38a..158361f 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -12,7 +12,8 @@ */
External (NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) + +OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -102,10 +103,6 @@
Offset (0xa0), CBMC, 32, // 0xa0 - coreboot mem console pointer - - /* ChromeOS specific */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> }
/* Set flag to enable USB charging in S3 */
-
Kyösti Mälkki (Code Review)