Change in coreboot[master]: mb/intel/shadowmountain: Disable xDCI

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51282 )

Change subject: mb/intel/shadowmountain: Disable xDCI
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mb/intel/shadowmountain: Disable xDCI

This patch disables the xDCI which is causing PC8 to PC10 state
transitions during sleep.

TEST: Confirmed that the transition is happening with this change.

Change-Id: I9bbf7b52c36954600d7e66f9b03fad39b8881a5f
Signed-off-by: Sugnan Prabhu S 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51282
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
Reviewed-by: Rizwan Qureshi 
Reviewed-by: Aamir Bohra 
---
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Rizwan Qureshi: Looks good to me, approved
  Subrata Banik: Looks good to me, approved
  Aamir Bohra: Looks good to me, approved

diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index f7ddaba..e9284f4 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -197,7 +197,7 @@
    	device pci 09.0 off end # NPK
    	device pci 0a.0 off end # Crash-log SRAM
    	device pci 0d.0 on  end # USB xHCI
-		device pci 0d.1 on  end # USB xDCI (OTG)
+		device pci 0d.1 off end # USB xDCI (OTG)
    	device pci 0d.2 on
    		chip drivers/intel/usb4/retimer
    			register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H19)"