Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30688
Change subject: [WIP] aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK ......................................................................
[WIP] aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK
Need to figure out better solution for AP_SIPI_VECTOR.
Change-Id: I22c172d577e6072562d8fcfa58145ec62473823e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/intel/socket_mPGA604/Makefile.inc A src/mainboard/aopen/dxplplusu/Makefile.inc A src/mainboard/aopen/dxplplusu/bootblock.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/bootblock.c M src/superio/smsc/lpc47m10x/Makefile.inc 9 files changed, 54 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/30688/1
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index a7cb99e..8d2bbcb 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -44,6 +44,7 @@
config AP_SIPI_VECTOR hex + default 0xffff0000 if C_ENVIRONMENT_BOOTBLOCK default 0xfffff000 help This must equal address of ap_sipi_vector from bootblock build. diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index ab0cf8a..ca2f7b3 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -10,6 +10,7 @@ select SSE select UDELAY_TSC select SIPI_VECTOR_IN_ROM + select C_ENVIRONMENT_BOOTBLOCK
# mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on @@ -26,4 +27,8 @@ hex default 0x4000
+config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + endif # CPU_INTEL_SOCKET_MPGA604 diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 371f7a6..9e3b8d7 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -7,6 +7,8 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading
-cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S +bootblock-y += ../car/p4-netburst/cache_as_ram.S +bootblock-y += ../car/bootblock.c + postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/mainboard/aopen/dxplplusu/Makefile.inc b/src/mainboard/aopen/dxplplusu/Makefile.inc new file mode 100644 index 0000000..0fedf5c --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/Makefile.inc @@ -0,0 +1,14 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c diff --git a/src/mainboard/aopen/dxplplusu/bootblock.c b/src/mainboard/aopen/dxplplusu/bootblock.c new file mode 100644 index 0000000..7c1d11d --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/bootblock.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Kyösti Mälkki kyosti.malkki@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp_def.h> +#include <superio/smsc/lpc47m10x/lpc47m10x.h> + +#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Get the serial port running and print a welcome banner */ + lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 827f6bb..cae178a 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -29,8 +29,4 @@ hex default 0xfef00000
-config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82801dx/bootblock.c" - endif diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index 7d87995..5ba2130 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -30,4 +30,6 @@
romstage-y += early_smbus.c
+bootblock-y += bootblock.c + endif diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c index 8ae419d..a5e48e5 100644 --- a/src/southbridge/intel/i82801dx/bootblock.c +++ b/src/southbridge/intel/i82801dx/bootblock.c @@ -11,9 +11,10 @@ * GNU General Public License for more details. */
+#include <cpu/intel/car/bootblock.h> #include <arch/io.h>
-static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { /* Set FWH IDs for 2 MB flash part. */ if (CONFIG_ROM_SIZE == 0x200000) diff --git a/src/superio/smsc/lpc47m10x/Makefile.inc b/src/superio/smsc/lpc47m10x/Makefile.inc index 0dd272c..278aa1e 100644 --- a/src/superio/smsc/lpc47m10x/Makefile.inc +++ b/src/superio/smsc/lpc47m10x/Makefile.inc @@ -18,5 +18,6 @@ ## GNU General Public License for more details. ##
+bootblock-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += superio.c
Hello Patrick Rudolph, Felix Held, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30688
to look at the new patch set (#2).
Change subject: [WIP] aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK ......................................................................
[WIP] aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK
Need to figure out better solution for AP_SIPI_VECTOR.
Change-Id: I22c172d577e6072562d8fcfa58145ec62473823e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/intel/socket_mPGA604/Makefile.inc M src/mainboard/aopen/dxplplusu/Kconfig A src/mainboard/aopen/dxplplusu/Makefile.inc A src/mainboard/aopen/dxplplusu/bootblock.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/bootblock.c 8 files changed, 56 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/30688/2
Hello Patrick Rudolph, Felix Held, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30688
to look at the new patch set (#3).
Change subject: aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK ......................................................................
aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK
This board is the only user of these ancient chipsets, so we'll do all in one go.
Also wipe out some extra headers.
Change-Id: I22c172d577e6072562d8fcfa58145ec62473823e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/intel/socket_mPGA604/Makefile.inc M src/mainboard/aopen/dxplplusu/Kconfig A src/mainboard/aopen/dxplplusu/Makefile.inc A src/mainboard/aopen/dxplplusu/bootblock.c M src/mainboard/aopen/dxplplusu/romstage.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/bootblock.c 9 files changed, 56 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/30688/3
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30688 )
Change subject: aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK ......................................................................
Patch Set 3: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30688 )
Change subject: aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK ......................................................................
aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK
This board is the only user of these ancient chipsets, so we'll do all in one go.
Also wipe out some extra headers.
Change-Id: I22c172d577e6072562d8fcfa58145ec62473823e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/30688 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/intel/socket_mPGA604/Makefile.inc M src/mainboard/aopen/dxplplusu/Kconfig A src/mainboard/aopen/dxplplusu/Makefile.inc A src/mainboard/aopen/dxplplusu/bootblock.c M src/mainboard/aopen/dxplplusu/romstage.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/bootblock.c 9 files changed, 56 insertions(+), 21 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index ab0cf8a..ca2f7b3 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -10,6 +10,7 @@ select SSE select UDELAY_TSC select SIPI_VECTOR_IN_ROM + select C_ENVIRONMENT_BOOTBLOCK
# mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on @@ -26,4 +27,8 @@ hex default 0x4000
+config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + endif # CPU_INTEL_SOCKET_MPGA604 diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 371f7a6..9e3b8d7 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -7,6 +7,8 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading
-cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S +bootblock-y += ../car/p4-netburst/cache_as_ram.S +bootblock-y += ../car/bootblock.c + postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index 85c45d5..3a729ce 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -29,6 +29,10 @@ int default 4
+config C_ENV_BOOTBLOCK_SIZE + hex + default 0x4000 + config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0x0 diff --git a/src/mainboard/aopen/dxplplusu/Makefile.inc b/src/mainboard/aopen/dxplplusu/Makefile.inc new file mode 100644 index 0000000..0fedf5c --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/Makefile.inc @@ -0,0 +1,14 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c diff --git a/src/mainboard/aopen/dxplplusu/bootblock.c b/src/mainboard/aopen/dxplplusu/bootblock.c new file mode 100644 index 0000000..f06f76e --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/bootblock.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Kyösti Mälkki kyosti.malkki@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp_def.h> +#include <superio/smsc/lpc47m10x/lpc47m10x.h> + +#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Get the serial port configured. */ + lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index f95c7f9..57538d6 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -14,22 +14,14 @@ */
#include <stdint.h> -#include <device/pci_def.h> #include <arch/io.h> -#include <stdlib.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h>
#include <southbridge/intel/i82801dx/i82801dx.h> #include <northbridge/intel/e7505/raminit.h>
-#include <device/pnp_def.h> -#include <superio/smsc/lpc47m10x/lpc47m10x.h> - -#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) - int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); @@ -46,13 +38,6 @@ }, };
- /* Get the serial port running and print a welcome banner */ - lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - /* If this is a warm boot, some initialization can be skipped */ if (!e7505_mch_is_ready()) { enable_smbus(); diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 5670e16..12640b3 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -31,8 +31,4 @@ hex default 0xfef00000
-config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82801dx/bootblock.c" - endif diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index 7d87995..5ba2130 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -30,4 +30,6 @@
romstage-y += early_smbus.c
+bootblock-y += bootblock.c + endif diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c index 8ae419d..a5e48e5 100644 --- a/src/southbridge/intel/i82801dx/bootblock.c +++ b/src/southbridge/intel/i82801dx/bootblock.c @@ -11,9 +11,10 @@ * GNU General Public License for more details. */
+#include <cpu/intel/car/bootblock.h> #include <arch/io.h>
-static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { /* Set FWH IDs for 2 MB flash part. */ if (CONFIG_ROM_SIZE == 0x200000)
-
Arthur Heymans (Code Review) -
Kyösti Mälkki (Code Review)