[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines

[Subrata Banik (Code Review)]

Attention is currently required from: Cliff Huang, Kapil Porwal, Paul Menzel, Pranava Y N.

Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email )

Change subject: soc/intel/ptl: Add GPE1 defines
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Patch Set 9:

(1 comment)

File src/soc/intel/pantherlake/include/soc/pm.h:

https://review.coreboot.org/c/coreboot/+/84297/comment/6ef7b961_3ce2fc5d?usp... :
PS9, Line 133: #if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)
> Subrata, if these 3 defines are here, we won't be using the defines in ./soc/intel/common/block/include/intelblocks/pmclib.h
>
> #if !CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)
> #define GPE1_STS(x) (0x0 + ((x) * 4))
> #define GPE1_EN(x) (0x0 + ((x) * 4))
> #define GPE1_REG_MAX 0
> #endif
>
> and ending up we will add GEP1 blocks in FADT.

You won't be using the code in FADT if you follow the suggetion shared by Felix (https://review.coreboot.org/c/coreboot/+/84103/comment/f0a82554_c1c0c50b/)

ideally GPE1_STATUS can be non-zero for PTL as this is SoC feature but a platform can decide (mainboard) if wish to use SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 or not. In that way

```
fadt->gpe1_blk = 0;
if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)) {
    fadt->gpe1_blk = pmbase + GPE1_STS(0);
    fadt->gpe1_blk_len = 2 * GPE1_REG_MAX * sizeof(uint32_t);
    /*
     * NOTE: gpe1 is after gpe0, which has _STS and _EN register sets.
     * gpe1_base is the starting bit offset for GPE1.
     */
    fadt->gpe1_base = fadt->gpe0_blk_len / 2 * 8;
}

```