build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29161 )
Change subject: src: Remove unneeded whitespace ......................................................................
Patch Set 15:
(98 comments)
https://review.coreboot.org/#/c/29161/15/src/cpu/amd/family_10h-family_15h/p... File src/cpu/amd/family_10h-family_15h/powernow_acpi.c:
https://review.coreboot.org/#/c/29161/15/src/cpu/amd/family_10h-family_15h/p... PS15, Line 229: * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit. line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/cpu/via/nano/nano_init.c File src/cpu/via/nano/nano_init.c:
https://review.coreboot.org/#/c/29161/15/src/cpu/via/nano/nano_init.c@125 PS15, Line 125: msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/db-ft3b-lc/BiosCa... File src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/db-ft3b-lc/BiosCa... PS15, Line 145: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/lamar/BiosCallOut... File src/mainboard/amd/lamar/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/lamar/BiosCallOut... PS15, Line 162: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/olivehill/BiosCal... File src/mainboard/amd/olivehill/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/olivehill/BiosCal... PS15, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/olivehillplus/Bio... File src/mainboard/amd/olivehillplus/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/olivehillplus/Bio... PS15, Line 128: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/parmer/BiosCallOu... File src/mainboard/amd/parmer/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/parmer/BiosCallOu... PS15, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheetah... File src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheetah... PS15, Line 109: current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheetah... File src/mainboard/amd/serengeti_cheetah_fam10/mptable.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheetah... PS15, Line 110: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheetah... PS15, Line 116: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheetah... PS15, Line 122: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheetah... PS15, Line 128: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheetah... PS15, Line 150: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheetah... PS15, Line 150: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheetah... PS15, Line 163: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheetah... PS15, Line 163: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/thatcher/BiosCall... File src/mainboard/amd/thatcher/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/thatcher/BiosCall... PS15, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/torpedo/gpio.c File src/mainboard/amd/torpedo/gpio.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/torpedo/gpio.c@94 PS15, Line 94: if (BoardType == 0) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/15/src/mainboard/bap/ode_e20XX/BiosCal... File src/mainboard/bap/ode_e20XX/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/bap/ode_e20XX/BiosCal... PS15, Line 117: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/bap/ode_e21XX/BiosCal... File src/mainboard/bap/ode_e21XX/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/bap/ode_e21XX/BiosCal... PS15, Line 130: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/biostar/a68n_5200/Bio... File src/mainboard/biostar/a68n_5200/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/biostar/a68n_5200/Bio... PS15, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/gizmosphere/gizmo/Oem... File src/mainboard/gizmosphere/gizmo/OemCustomize.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/gizmosphere/gizmo/Oem... PS15, Line 126: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/gizmosphere/gizmo2/Bi... File src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/gizmosphere/gizmo2/Bi... PS15, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/hp/pavilion_m6_1035dx... File src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/hp/pavilion_m6_1035dx... PS15, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/lenovo/g505s/BiosCall... File src/mainboard/lenovo/g505s/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/lenovo/g505s/BiosCall... PS15, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/lenovo/t60/smihandler... File src/mainboard/lenovo/t60/smihandler.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/lenovo/t60/smihandler... PS15, Line 52: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/lenovo/z61t/smihandle... File src/mainboard/lenovo/z61t/smihandler.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/lenovo/z61t/smihandle... PS15, Line 53: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-a... File src/mainboard/lippert/frontrunner-af/mainboard.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-a... PS15, Line 68: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-a... PS15, Line 69: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-a... PS15, Line 72: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-a... PS15, Line 74: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-a... PS15, Line 76: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-a... PS15, Line 77: FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-a... PS15, Line 78: FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/toucan-af/mai... File src/mainboard/lippert/toucan-af/mainboard.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/toucan-af/mai... PS15, Line 36: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/toucan-af/mai... PS15, Line 37: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/toucan-af/mai... PS15, Line 41: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/toucan-af/mai... PS15, Line 43: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/toucan-af/mai... PS15, Line 45: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/15/src/mainboard/msi/ms9652_fam10/get_... File src/mainboard/msi/ms9652_fam10/get_bus_conf.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/msi/ms9652_fam10/get_... PS15, Line 104: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/msi/ms9652_fam10/get_... PS15, Line 109: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/pcengines/apu1/OemCus... File src/mainboard/pcengines/apu1/OemCustomize.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/pcengines/apu1/OemCus... PS15, Line 111: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/pcengines/apu2/mainbo... File src/mainboard/pcengines/apu2/mainboard.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/pcengines/apu2/mainbo... PS15, Line 175: pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/supermicro/h8dmr_fam1... File src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/supermicro/h8dmr_fam1... PS15, Line 102: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/supermicro/h8dmr_fam1... PS15, Line 107: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/supermicro/h8qme_fam1... File src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/supermicro/h8qme_fam1... PS15, Line 108: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/supermicro/h8qme_fam1... PS15, Line 113: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/tyan/s2912_fam10/get_... File src/mainboard/tyan/s2912_fam10/get_bus_conf.c:
https://review.coreboot.org/#/c/29161/15/src/mainboard/tyan/s2912_fam10/get_... PS15, Line 101: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/mainboard/tyan/s2912_fam10/get_... PS15, Line 106: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/northbridge/amd/agesa/family12/... File src/northbridge/amd/agesa/family12/dimmSpd.c:
https://review.coreboot.org/#/c/29161/15/src/northbridge/amd/agesa/family12/... PS15, Line 58: ) please, no spaces at the start of a line
https://review.coreboot.org/#/c/29161/15/src/northbridge/intel/fsp_rangeley/... File src/northbridge/intel/fsp_rangeley/northbridge.c:
https://review.coreboot.org/#/c/29161/15/src/northbridge/intel/fsp_rangeley/... PS15, Line 134: ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c File src/soc/broadcom/cygnus/ddr_init.c:
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 73: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 75: (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 78: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 83: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 85: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 87: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 91: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 93: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 96: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 98: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 100: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 104: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 106: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 113: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 118: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 131: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 137: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 143: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff)); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 149: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 156: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 167: #define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 473: reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25)); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 479: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 479: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 485: if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) { line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 1000: reg32_write(reg,val); space required after that ',' (ctx:VxV)
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c@... PS15, Line 1403: printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/phy_reg_acc... File src/soc/broadcom/cygnus/phy_reg_access.c:
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/phy_reg_acc... PS15, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/phy_reg_acc... PS15, Line 27: ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/intel/baytrail/perf_power.c File src/soc/intel/baytrail/perf_power.c:
https://review.coreboot.org/#/c/29161/15/src/soc/intel/baytrail/perf_power.c... PS15, Line 224: E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/soc/intel/fsp_baytrail/northclu... File src/soc/intel/fsp_baytrail/northcluster.c:
https://review.coreboot.org/#/c/29161/15/src/soc/intel/fsp_baytrail/northclu... PS15, Line 161: ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan.... File src/southbridge/amd/cimx/sb800/fan.c:
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan.... PS15, Line 234: sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan.... PS15, Line 238: sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan.... PS15, Line 252: sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan.... PS15, Line 256: sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan.... PS15, Line 270: sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan.... PS15, Line 274: sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan.... PS15, Line 288: sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan.... PS15, Line 292: sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c:
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/rs780/gfx.c@250 PS15, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/rs780/gfx.c@250 PS15, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/sb700/sata.c File src/southbridge/amd/sb700/sata.c:
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/sb700/sata.c@47... PS15, Line 473: (i % 2) ? "Slave" : "Master", i); line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/sr5650/pcie.c File src/southbridge/amd/sr5650/pcie.c:
https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/sr5650/pcie.c@8... PS15, Line 809: if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/15/src/southbridge/intel/bd82x6x/early... File src/southbridge/intel/bd82x6x/early_usb.c:
https://review.coreboot.org/#/c/29161/15/src/southbridge/intel/bd82x6x/early... PS15, Line 38: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/southbridge/intel/fsp_bd82x6x/e... File src/southbridge/intel/fsp_bd82x6x/early_init.c:
https://review.coreboot.org/#/c/29161/15/src/southbridge/intel/fsp_bd82x6x/e... PS15, Line 145: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/southbridge/intel/fsp_i89xx/ear... File src/southbridge/intel/fsp_i89xx/early_init.c:
https://review.coreboot.org/#/c/29161/15/src/southbridge/intel/fsp_i89xx/ear... PS15, Line 32: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters
https://review.coreboot.org/#/c/29161/15/src/southbridge/nvidia/ck804/early_... File src/southbridge/nvidia/ck804/early_setup.c:
https://review.coreboot.org/#/c/29161/15/src/southbridge/nvidia/ck804/early_... PS15, Line 258: RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), line over 80 characters