[S] Change in coreboot[main]: soc/intel/xeon_sp: Work around DPR silicon bug

[Patrick Rudolph (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Paul Menzel, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, [e-mail].

Hello Christian Walter, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, build bot (Jenkins), [e-mail],

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85829?usp=email

to look at the new patch set (#4).

Change subject: soc/intel/xeon_sp: Work around DPR silicon bug
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soc/intel/xeon_sp: Work around DPR silicon bug

On first batch of Intel Xeon-SP 10nm CPU the DPR register is affected
by a silicon bug, where the TOP bits read as 0, which isn't possible
according to the EDS. Currently the code also assumes that it's never
zero and calculates the DPR size using the assigned address. By using
0 as TOP address it overflows and breaks boot due to an overly large
MMIO window.

Add a check for the silicon bug and use TSEG base like it's already
done on Snow Ridge, which is also a 10nm Xeon CPU affected by the
same bug.

Fixes negative size being calculated for DPR.
TEST: Xeon ICX-SP boots to Linux.

Change-Id: Ia090013721053ae85001a3e7d47ad2b1ec9a3203
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/snowridge/systemagent.c
M src/soc/intel/xeon_sp/uncore.c
2 files changed, 33 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85829/4