Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating - coreboot-gerrit

11 Apr 2022


      Attention is currently required from: Subrata Banik, Paul Menzel, Sridhar Siricilla, Angel Pons, Kane Chen.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 )
Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
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Patch Set 9: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d
Gerrit-Change-Number: 63293
Gerrit-PatchSet: 9
Gerrit-Owner: Sridhar Siricilla sridhar.siricilla@intel.com
Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Kane Chen kane.chen@intel.com
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