Change in coreboot[master]: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC

[Michael Niewöhner (Code Review)]

Hello  Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46461

to look at the new patch set (#8).

Change subject: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
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soc/intel/skl: replace conditional on dt option reading CPUID for CPPC

Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead
of relying on the devicetree option `speed_shift_enable`, that is going
to be dropped.

Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F

Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e
Signed-off-by: Michael Niewöhner 
---
M src/soc/intel/skylake/acpi.c
1 file changed, 4 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46461/8