Change in coreboot[master]: soc/intel/jasperlake: Update CpuRatio settings

[Kaiyen Chang (Code Review)]

Attention is currently required from: Kaiyen Chang.
Hello Kaiyen Chang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/52029

to review the following change.

Change subject: soc/intel/jasperlake: Update CpuRatio settings
......................................................................

soc/intel/jasperlake: Update CpuRatio settings

An extra reset is observed on JSL platform while the flex ratio in CPU
Straps is set to a non-zero value. The root cause is that the config of
CpuRatio on JSL is fixed to zero in fsp_param.c. While FSP finds the
value of CpuRatio from m_cfg is inconsistent with the value from CPU
straps, it will invoke a system reset to apply the value from m_cfg.

This change adds a mechanism to set CpuRatio to allowed maximum
processor non-turbo ratio (from CPU straps) when cpu_ratio_override is
not set, or overriding CpuRatio with the value of cpu_ratio_override
when cpu_ratio_override is set to a non-zero value instead of just
fixing CpuRatio to zero.

BUG=b:181588337
BRANCH=None
TEST=Boot JSL platform and observe there is no extra reset in meminit.

Change-Id: I20b9d5620b8e394201e82185eb28b67d6702b2d5
---
M src/soc/intel/jasperlake/romstage/fsp_params.c
1 file changed, 12 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/52029/1

diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index cd70807..31c9f6f 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -2,9 +2,11 @@

#include <assert.h>
 #include <console/console.h>
+#include <cpu/x86/msr.h>
 #include <device/device.h>
 #include <fsp/util.h>
 #include <soc/iomap.h>
+#include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
@@ -29,6 +31,16 @@
    m_cfg->SaGv = config->SaGv;
    m_cfg->RMT = config->RMT;

+	/* CpuRatio Settings */
+	if (config->cpu_ratio_override) {
+		m_cfg->CpuRatio = config->cpu_ratio_override;
+	} else {
+		/* Set CpuRatio to match existing MSR value */
+		msr_t flex_ratio;
+		flex_ratio = rdmsr(MSR_FLEX_RATIO);
+		m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
+	}
+
    /* PCIe root port configuration */
    for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
    	if (config->PcieRpEnable[i])
@@ -52,9 +64,6 @@
    /* Disable BIOS Guard */
    m_cfg->BiosGuard = 0;

-	/* Set CPU Ratio */
-	m_cfg->CpuRatio = 0;
-
    /* Set debug interface flags */
    m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
    	DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO;