Patch set updated for coreboot: 99feee2 southbridge/intel/bd82x6x: add option to not enable display audio codec
Nicolas Reinecke (nr@das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8303
-gerrit
commit 99feee2a51ae524d02a040aae51b8baaa6826462 Author: Nicolas Reinecke nr@das-labor.org Date: Wed Feb 4 22:25:01 2015 +0100
southbridge/intel/bd82x6x: add option to not enable display audio codec
Some Thinkpads like T420s or T520 with discrete GPU have only VGA and LVDS conntected to the IGP. For this devices is it usefull to have an option to not enable audio codec. The audio dev shows up in linux as hdmi codec but is complete useless.
Change-Id: Iaa60b6d4c3c98ec9616ea0ef43913bbcf0d315da Signed-off-by: Nicolas Reinecke nr@das-labor.org --- src/mainboard/lenovo/t420s/devicetree.cb | 3 +++ src/mainboard/lenovo/t520/devicetree.cb | 3 +++ src/southbridge/intel/bd82x6x/azalia.c | 23 +++++++++++------------ src/southbridge/intel/bd82x6x/chip.h | 3 +++ 4 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 990b576..5aa8f0a 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -61,6 +61,9 @@ chip northbridge/intel/sandybridge # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3"
+ # not enable audio codec on digital video outups. (for discrete gpu models) + register "azalia_video_codec_not_enable" = "1" + register "gen1_dec" = "0x7c1601" register "gen2_dec" = "0x0c15e1" register "gen4_dec" = "0x0c06a1" diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index d2a4d6b..0fccaa8 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -57,6 +57,9 @@ chip northbridge/intel/sandybridge # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3"
+ # not enable audio codec on digital video outups. (for discrete gpu models) + register "azalia_video_codec_not_enable" = "1" + register "gen1_dec" = "0x7c1601" register "gen2_dec" = "0x0c15e1" register "gen4_dec" = "0x0c06a1" diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index bef88ab..c1feb8f 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -228,6 +228,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void azalia_init(struct device *dev) { + struct southbridge_intel_bd82x6x_config *config = dev->chip_info; u32 base; struct resource *res; u32 codec_mask; @@ -267,22 +268,20 @@ static void azalia_init(struct device *dev) reg32 |= (1 << 31); pci_write_config32(dev, 0x120, reg32);
- // Enable HDMI codec: - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 1); - pci_write_config32(dev, 0xc4, reg32); + if (!(config->azalia_video_codec_not_enable)) { + // Enable HDMI codec: + reg32 = pci_read_config32(dev, 0xc4); + reg32 |= (1 << 1); + pci_write_config32(dev, 0xc4, reg32);
- reg8 = pci_read_config8(dev, 0x43); - reg8 |= (1 << 6); - pci_write_config8(dev, 0x43, reg8); + reg8 = pci_read_config8(dev, 0x43); + reg8 |= (1 << 6); + pci_write_config8(dev, 0x43, reg8); + }
/* Additional programming steps */ reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 13); - pci_write_config32(dev, 0xc4, reg32); - - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 10); + reg32 |= (1 << 13) | (1 << 10); pci_write_config32(dev, 0xc4, reg32);
reg32 = pci_read_config32(dev, 0xd0); diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index f4be82d..dab5ccc 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -94,6 +94,9 @@ struct southbridge_intel_bd82x6x_config { uint32_t xhci_switchable_ports; /* Ports which support SuperSpeed (USB 3.0 additional lanes). */ uint32_t superspeed_capable_ports; + + /* do not enable audio codec on digital video outputs */ + uint8_t azalia_video_codec_not_enable; };
#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
-
Nicolas Reinecke