Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29771 )
Change subject: intelblocks/cpu: Add function to set CPU clock to minimum value
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/29771/3/src/soc/intel/common/block/cpu/cpuli...
File src/soc/intel/common/block/cpu/cpulib.c:
https://review.coreboot.org/#/c/29771/3/src/soc/intel/common/block/cpu/cpuli...
PS3, Line 144: * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with the value
nit: bit 15:8
If I have a look at the APL EDS Vol. 2, it tells me that bit 15 is reserved.
--
To view, visit
https://review.coreboot.org/c/coreboot/+/29771
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549
Gerrit-Change-Number: 29771
Gerrit-PatchSet: 3
Gerrit-Owner: Werner Zeh
werner.zeh@siemens.com
Gerrit-Reviewer: Aaron Durbin
adurbin@gmail.com
Gerrit-Reviewer: Huang Jin
huang.jin@intel.com
Gerrit-Reviewer: Mario Scheithauer
mario.scheithauer@siemens.com
Gerrit-Reviewer: Nico Huber
nico.h@gmx.de
Gerrit-Reviewer: Werner Zeh
werner.zeh@siemens.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-Comment-Date: Thu, 22 Nov 2018 05:20:31 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Huang Jin
huang.jin@intel.com
Gerrit-MessageType: comment