Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34818 )
Change subject: soc/intel/common: Fix typo mistake in cache_as_ram.S ......................................................................
soc/intel/common: Fix typo mistake in cache_as_ram.S
Change-Id: I14c0e87012bdbaaff50844ed097b66e2221b1e08 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/34818/1
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index b1648e8..d5f5081 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -365,7 +365,7 @@ jnz find_llc_subleaf
/* - * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE + * Set MSR 0xC91 IA32_L3_MASK_1 = 0xE/0xFE/0xFFE/0xFFFE * for 4/8/16 way of LLC */ shr $22, %ebx
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34818 )
Change subject: soc/intel/common: Fix typo mistake in cache_as_ram.S ......................................................................
Patch Set 1: Code-Review+2
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34818 )
Change subject: soc/intel/common: Fix typo mistake in cache_as_ram.S ......................................................................
Patch Set 1: Code-Review+2
Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34818 )
Change subject: soc/intel/common: Fix typo mistake in cache_as_ram.S ......................................................................
soc/intel/common: Fix typo mistake in cache_as_ram.S
Change-Id: I14c0e87012bdbaaff50844ed097b66e2221b1e08 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34818 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: V Sowmya v.sowmya@intel.com --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved V Sowmya: Looks good to me, approved
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index b1648e8..d5f5081 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -365,7 +365,7 @@ jnz find_llc_subleaf
/* - * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE + * Set MSR 0xC91 IA32_L3_MASK_1 = 0xE/0xFE/0xFFE/0xFFFE * for 4/8/16 way of LLC */ shr $22, %ebx
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Arthur Heymans (Code Review) -
Subrata Banik (Code Review)
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V Sowmya (Code Review)