Change in ...coreboot[master]: soc/intel/cannonlake: Fix pcie clock number

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32672

Change subject: soc/intel/cannonlake: Fix pcie clock number
......................................................................

soc/intel/cannonlake: Fix pcie clock number

Cannonlake PCH LP have total 6 pcie clocks and Cannonlake PCH H have
total 16 pcie clocks. It is different with pcie root port numbers.

BUG=CID 1381814
TEST=Build and boot up fine on sarien platform.

Signed-off-by: Lijian Zhao 
Change-Id: I909b5b584c596e6fe878ffe24d9cabc53c4576ed
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/chip.h
2 files changed, 7 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32672/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index c06b91e..e524275 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -183,6 +183,11 @@
    default 24 if SOC_INTEL_CANNONLAKE_PCH_H
    default 16

+config MAX_PCIE_CLOCKS
+	int
+	default 16 if SOC_INTEL_CANNONLAKE_PCH_H
+	default 6
+
 config SMM_TSEG_SIZE
    hex
    default 0x800000
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index b17df4b..f34528a 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -168,10 +168,10 @@
    /* PCIe output clocks type to Pcie devices.
     * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
     * 0xFF: not used */
-	uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];
+	uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
    /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
     * clksrc. */
-	uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
+	uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
    /* PCIe LTR(Latency Tolerance Reporting) mechanism */
    uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
    /* Enable/Disable HotPlug support for Root Port */

[John Zhao (Code Review)]

John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32672 )

Change subject: soc/intel/cannonlake: Fix pcie clock number
......................................................................

Patch Set 1: Code-Review+1

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32672 )

Change subject: soc/intel/cannonlake: Fix pcie clock number
......................................................................

Patch Set 1: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32672 )

Change subject: soc/intel/cannonlake: Fix pcie clock number
......................................................................

Patch Set 1: Code-Review+2

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32672 )

Change subject: soc/intel/cannonlake: Fix pcie clock number
......................................................................

Patch Set 1: Code-Review+2

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32672 )

Change subject: soc/intel/cannonlake: Fix pcie clock number
......................................................................

soc/intel/cannonlake: Fix pcie clock number

Cannonlake PCH LP have total 6 pcie clocks and Cannonlake PCH H have
total 16 pcie clocks. It is different with pcie root port numbers.

BUG=CID 1381814
TEST=Build and boot up fine on sarien platform.

Signed-off-by: Lijian Zhao 
Change-Id: I909b5b584c596e6fe878ffe24d9cabc53c4576ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32672
Tested-by: build bot (Jenkins) 
Reviewed-by: John Zhao 
Reviewed-by: Nico Huber 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Subrata Banik 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/chip.h
2 files changed, 7 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Furquan Shaikh: Looks good to me, approved
  John Zhao: Looks good to me, but someone else must approve
  Subrata Banik: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index c06b91e..e524275 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -183,6 +183,11 @@
    default 24 if SOC_INTEL_CANNONLAKE_PCH_H
    default 16

+config MAX_PCIE_CLOCKS
+	int
+	default 16 if SOC_INTEL_CANNONLAKE_PCH_H
+	default 6
+
 config SMM_TSEG_SIZE
    hex
    default 0x800000
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index b17df4b..f34528a 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -168,10 +168,10 @@
    /* PCIe output clocks type to Pcie devices.
     * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
     * 0xFF: not used */
-	uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];
+	uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
    /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
     * clksrc. */
-	uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
+	uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
    /* PCIe LTR(Latency Tolerance Reporting) mechanism */
    uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
    /* Enable/Disable HotPlug support for Root Port */