Attention is currently required from: Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Sukumar Ghorai, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi. Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 )
Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates ......................................................................
Patch Set 23:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49766/comment/92c1dc4b_cd7ee1bb PS9, Line 7: Disable S0i3.2 & S0i3.3 substates : : S0i3.2 and S0i3.3 are applicable only if wake on voice is : disabled. As per Platform Design Guide, S0i3.2 and S0i3.3 : substates need to be disabled for Tigerlake.
This needs update
Hi Furquan, what would be the right text to use for commit message?
https://review.coreboot.org/c/coreboot/+/49766/comment/b1854959_b459efe0 PS9, Line 12:
Can you please check what is the lowest power state reported by coreboot and actually observed on vo […]
We see S0i3.2 as the lowest state on all the TGL based devices.
File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/49766/comment/a5ce9b5b_5bc4ba1f PS9, Line 502: enabled
Rather than saying "enabled", I think it should say "Mainboard design uses external clock gating" si […]
Ok. Updated it.
https://review.coreboot.org/c/coreboot/+/49766/comment/b3dc7b82_557deed9 PS9, Line 506: ExternalClkGated
nit: use external_clk_gated instead of ExternalClkGated. […]
I did not know this. Makes sense and its easy to now distinguish between FSP UPDs and Coreboot specific board options.
File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/49766/comment/c2e879b2_3429d4e7 PS9, Line 67: recommended
It would be good to capture in commit message what "recommended" means i.e. […]
Ok.