New subject: Change in coreboot[master]: mediatek/mt8183: Add display driver

19 Feb 2019

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31478
Change subject: mediatek/mt8183: Add display driver
......................................................................
mediatek/mt8183: Add display driver
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Ic4aecc58d081f14f5d136b9ff8e813e6f40f78eb
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com
---
M src/mainboard/google/kukui/mainboard.c
M src/soc/mediatek/mt8183/Makefile.inc
A src/soc/mediatek/mt8183/ddp.c
M src/soc/mediatek/mt8183/include/soc/addressmap.h
A src/soc/mediatek/mt8183/include/soc/ddp.h
5 files changed, 602 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/31478/1

diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c
index e1d8f5f..a089236 100644
--- a/src/mainboard/google/kukui/mainboard.c
+++ b/src/mainboard/google/kukui/mainboard.c
@@ -13,9 +13,14 @@
  * GNU General Public License for more details.
  */
+#include <bootmode.h>
+#include <console/console.h>
 #include <device/device.h>
+#include <edid.h>
+#include <soc/ddp.h>
 #include <soc/gpio.h>
 #include <soc/mmu_operations.h>
+#include <soc/mtcmos.h>
 #include <soc/usb.h>
static void configure_emmc(void)
@@ -37,8 +42,36 @@
    setup_usb_host();
 }
+static void display_startup(void)
+{
+	int ret = 0;
+	struct edid edid;
+
+	edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
+
+	mtk_ddp_init();
+	if (ret < 0) {
+		printk(BIOS_ERR, "dsi init fail\n");
+		return;
+	}
+
+	mtk_ddp_mode_set(&edid);
+
+	set_vbe_mode_info_valid(&edid, (uintptr_t)0);
+}
+
 static void mainboard_init(struct device *dev)
 {
+	if (display_init_required()) {
+		printk(BIOS_INFO, "start display init.\n");
+		mtcmos_display_power_on();
+		mtcmos_protect_display_bus();
+
+		display_startup();
+	} else {
+		printk(BIOS_INFO, "Skipping display init.\n");
+	}
+
    configure_emmc();
    configure_usb();
 }
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index 5770a83..225a969 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -49,6 +49,7 @@
 ramstage-y += ../common/uart.c
 ramstage-y += ../common/usb.c
 ramstage-y += ../common/wdt.c
+ramstage-y += ddp.c
CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include
 CPPFLAGS_common += -Isrc/soc/mediatek/common/include
diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c
new file mode 100644
index 0000000..2e2c0d2
--- /dev/null
+++ b/src/soc/mediatek/mt8183/ddp.c
@@ -0,0 +1,229 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <edid.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stddef.h>
+#include <soc/addressmap.h>
+#include <soc/ddp.h>
+
+#define RDMA_FIFO_PSEUDO_SIZE(bytes)            (((bytes) / 16) << 16)
+#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
+
+static void disp_config_main_path_connection(void)
+{
+	write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_OVL0_2L);
+
+	write32(&mmsys_cfg->disp_ovl0_2l_mout_en, OVL0_2L_MOUT_EN_DISP_PATH0);
+
+	write32(&mmsys_cfg->disp_path0_sel_in, DISP_PATH0_SEL_IN_OVL0_2L);
+
+	write32(&mmsys_cfg->disp_rdma0_sout_sel_in, RDMA0_SOUT_SEL_IN_COLOR);
+
+	write32(&mmsys_cfg->disp_dither0_mout_en, DITHER0_MOUT_EN_DISP_DSI0);
+
+	write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0_MOUT);
+}
+
+static void disp_config_main_path_mutex(void)
+{
+	write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH);
+
+	/* Clock source from DSI0 */
+	write32(&disp_mutex->mutex[0].ctl,
+		MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6));
+	write32(&disp_mutex->mutex[0].en, BIT(0));
+}
+
+static void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color)
+{
+	write32(&disp_ovl[idx]->roi_size, height << 16 | width);
+	write32(&disp_ovl[idx]->roi_bgclr, color);
+}
+
+static void ovl_layer_enable(u32 idx)
+{
+	write32(&disp_ovl[idx]->rdma[0].ctrl, BIT(0));
+	write32(&disp_ovl[idx]->rdma[0].mem_gmc_setting, RDMA_MEM_GMC);
+
+	setbits_le32(&disp_ovl[idx]->src_con, BIT(0));
+}
+
+static void ovl_bgclr_in_sel(u32 idx)
+{
+	setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2));
+}
+
+static void rdma_start(u32 idx)
+{
+	setbits_le32(&disp_rdma[idx]->global_con, RDMA_ENGINE_EN);
+}
+
+static void rdma_config(u32 idx, u32 width, u32 height, u32 vrefresh)
+{
+	u32 threshold;
+	u32 reg;
+	u32 fifo_size;
+
+	/* Config width */
+	clrsetbits_le32(&disp_rdma[idx]->size_con_0, 0x1FFF, width);
+
+	/* Config height */
+	clrsetbits_le32(&disp_rdma[idx]->size_con_1, 0xFFFFF, height);
+
+	/*
+	 * Enable FIFO underflow since DSI and DPI can't be blocked. Keep the
+	 * FIFO pseudo size reset default of 8 KiB. Set the output threshold to
+	 * 6 microseconds with 7/6 overhead to account for blanking, and with a
+	 * pixel depth of 4 bytes:
+	 */
+
+	fifo_size = RDMA_FIFO_SIZE_0 * KiB;
+
+	threshold = width * height * vrefresh * 4 * 7 / 1000000;
+
+	if (threshold > fifo_size)
+		threshold = fifo_size;
+
+	reg = RDMA_FIFO_UNDERFLOW_EN |
+	      RDMA_FIFO_PSEUDO_SIZE(fifo_size) |
+	      RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
+
+	write32(&disp_rdma[idx]->fifo_con, reg);
+}
+
+static void color_start(u32 width, u32 height)
+{
+	write32(&disp_color->width, width);
+	write32(&disp_color->height, height);
+	write32(&disp_color->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL);
+	write32(&disp_color->start, BIT(0));
+}
+
+static void aal_start(u32 width, u32 height)
+{
+	write32(&disp_aal->size, height << 16 | width);
+	write32(&disp_aal->en, PQ_EN);
+}
+
+static void ccorr_start(u32 width, u32 height)
+{
+	write32(&disp_ccorr->size, height << 16 | width);
+	write32(&disp_ccorr->cfg, PQ_RELAY_MODE);
+	write32(&disp_ccorr->en, PQ_EN);
+}
+
+static void dither_start(u32 width, u32 height)
+{
+	write32(&disp_dither->size, height << 16 | width);
+	write32(&disp_dither->cfg, PQ_RELAY_MODE);
+	write32(&disp_dither->en, PQ_EN);
+}
+
+static void gamma_start(u32 width, u32 height)
+{
+	write32(&disp_gamma->size, height << 16 | width);
+	write32(&disp_gamma->en, PQ_EN);
+}
+
+static void ovl_layer_config(u32 idx, u32 fmt, u32 bpp, u32 width, u32 height)
+{
+	write32(&disp_ovl[idx]->layer[0].con, fmt << 12);
+	write32(&disp_ovl[idx]->layer[0].src_size, height << 16 | width);
+	write32(&disp_ovl[idx]->layer[0].pitch, (width * bpp) & 0xFFFF);
+
+	ovl_layer_enable(idx);
+}
+
+static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh)
+{
+	u32 idx = 0;
+
+	/* Setup OVL */
+	for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) {
+		u32 color = 0;
+
+		if (idx == 0)
+			color = 0xFF0000FF;
+
+		ovl_set_roi(idx, width, height, color);
+	}
+
+	/* Setup RDMA0 */
+	idx = 0;
+	rdma_config(idx, width, height, vrefresh);
+
+	/* Setup Color */
+	color_start(width, height);
+
+	/* Setup CCORR */
+	ccorr_start(width, height);
+
+	/* Setup AAL */
+	aal_start(width, height);
+
+	/* Setup GAMMA */
+	gamma_start(width, height);
+
+	/* Setup DITHER */
+	dither_start(width, height);
+
+	/* Setup main path connection */
+	disp_config_main_path_connection();
+
+	/* Setup main path mutex */
+	disp_config_main_path_mutex();
+}
+
+static void disp_clock_on(void)
+{
+	clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL);
+
+	clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 |
+						CG_CON1_DISP_DSI0_INTERFACE);
+}
+
+static void disp_m4u_port_off(void)
+{
+	write32((void *)(SMI_LARB0 + 0x380), 0);
+}
+
+void mtk_ddp_init(void)
+{
+	disp_clock_on();
+	disp_m4u_port_off();
+}
+
+void mtk_ddp_mode_set(const struct edid *edid)
+{
+	u32 fmt = OVL_INFMT_RGBA8888;
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 idx = 0;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh = edid->mode.refresh;
+
+	main_disp_path_setup(width, height, vrefresh);
+
+	rdma_start(idx);
+
+	ovl_layer_config(idx, fmt, bpp, width, height);
+
+	ovl_bgclr_in_sel(idx+1);
+}
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index d41b2b9..88653eb 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -53,6 +53,19 @@
    IOCFG_LT_BASE		= IO_PHYS + 0x01F20000,
    IOCFG_TL_BASE		= IO_PHYS + 0x01F30000,
    SSUSB_SIF_BASE		= IO_PHYS + 0x01F40300,
+	MMSYS_BASE              = IO_PHYS + 0x04000000,
+	DISP_OVL0_BASE          = IO_PHYS + 0x04008000,
+	DISP_OVL0_2L_BASE       = IO_PHYS + 0x04009000,
+	DISP_OVL1_2L_BASE       = IO_PHYS + 0x0400A000,
+	DISP_RDMA0_BASE         = IO_PHYS + 0x0400B000,
+	DISP_RDMA1_BASE         = IO_PHYS + 0x0400C000,
+	DISP_COLOR0_BASE        = IO_PHYS + 0x0400E000,
+	DISP_CCORR0_BASE        = IO_PHYS + 0x0400F000,
+	DISP_AAL0_BASE          = IO_PHYS + 0x04010000,
+	DISP_GAMMA0_BASE        = IO_PHYS + 0x04011000,
+	DISP_DITHER0_BASE       = IO_PHYS + 0x04012000,
+	DISP_MUTEX_BASE         = IO_PHYS + 0x04016000,
+	SMI_LARB0               = IO_PHYS + 0x04017000,
    SMI_BASE		= IO_PHYS + 0x04019000,
 };
diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h
new file mode 100644
index 0000000..38f66e8
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/ddp.h
@@ -0,0 +1,326 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DDP_REG_H_
+#define _DDP_REG_H_
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+#define MAIN_PATH_OVL_NR 2
+
+struct mmsys_cfg_regs {
+	u32 reserved_0x000[64];		/* 0x000 */
+	u32 mmsys_cg_con0;		/* 0x100 */
+	u32 mmsys_cg_set0;		/* 0x104 */
+	u32 mmsys_cg_clr0;		/* 0x108 */
+	u32 reserved_0x10C;		/* 0x10C */
+	u32 mmsys_cg_con1;		/* 0x110 */
+	u32 mmsys_cg_set1;		/* 0x114 */
+	u32 mmsys_cg_clr1;		/* 0x118 */
+	u32 reserved_0x11C[889];	/* 0x11C */
+	u32 disp_ovl0_mout_en;		/* 0xF00 */
+	u32 disp_ovl0_2l_mout_en; 	/* 0xF04 */
+	u32 disp_ovl1_2l_mout_en; 	/* 0xF08 */
+	u32 disp_dither0_mout_en; 	/* 0xF0C */
+	u32 reserved_0xF10[5];		/* 0xF10 - 0xF20 */
+	u32 disp_path0_sel_in; 		/* 0xF24 */
+	u32 reserved_0xF28;		/* 0xF28 */
+	u32 dsi0_sel_in;		/* 0xF2C */
+	u32 dpi0_sel_in;		/* 0xF30 */
+	u32 reserved_0xF34;		/* 0xF34 */
+	u32 disp_ovl0_2l_sel_in;	/* 0xF38 */
+	u32 reserved_0xF3C[5];		/* 0xF3C - 0xF4C */
+	u32 disp_rdma0_sout_sel_in;	/* 0xF50 */
+	u32 disp_rdma1_sout_sel_in;	/* 0xF54 */
+	u32 reserved_0xF58[3];		/* 0xF58 - 0xF60 */
+	u32 dpi0_sel_sout_sel_in;	/* 0xF64 */
+};
+
+check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100);
+check_member(mmsys_cfg_regs, reserved_0x11C, 0x11C);
+check_member(mmsys_cfg_regs, disp_ovl0_mout_en, 0xF00);
+check_member(mmsys_cfg_regs, reserved_0xF10, 0xF10);
+check_member(mmsys_cfg_regs, disp_path0_sel_in, 0xF24);
+check_member(mmsys_cfg_regs, disp_ovl0_2l_sel_in, 0xF38);
+check_member(mmsys_cfg_regs, reserved_0xF3C, 0xF3C);
+check_member(mmsys_cfg_regs, disp_rdma0_sout_sel_in, 0xF50);
+check_member(mmsys_cfg_regs, dpi0_sel_sout_sel_in, 0xF64);
+static struct mmsys_cfg_regs *const mmsys_cfg =
+	(void *)MMSYS_BASE;
+
+
+/* DISP_REG_CONFIG_MMSYS_CG_CON0
+   Configures free-run clock gating 0
+	0: Enable clock
+	1: Clock gating  */
+enum {
+	CG_CON0_SMI_COMMON  	= BIT(0),
+	CG_CON0_SMI_LARB0   	= BIT(1),
+	CG_CON0_GALS_COMMON0   	= BIT(3),
+	CG_CON0_GALS_COMMON1   	= BIT(4),
+	CG_CON0_DISP_OVL0	= BIT(20),
+	CG_CON0_DISP_OVL0_2L	= BIT(21),
+	CG_CON0_DISP_OVL1_2L	= BIT(22),
+	CG_CON0_DISP_RDMA0  	= BIT(23),
+	CG_CON0_DISP_RDMA1  	= BIT(24),
+	CG_CON0_DISP_WDMA0  	= BIT(25),
+	CG_CON0_DISP_COLOR0 	= BIT(26),
+	CG_CON0_DISP_CCORR0 	= BIT(27),
+	CG_CON0_DISP_AAL0    	= BIT(28),
+	CG_CON0_DISP_GAMMA0  	= BIT(29),
+	CG_CON0_DISP_DITHER0	= BIT(30),
+	CG_CON0_DISP_ALL	= CG_CON0_SMI_COMMON |
+				  CG_CON0_SMI_LARB0 |
+				  CG_CON0_GALS_COMMON0 |
+				  CG_CON0_GALS_COMMON1 |
+				  CG_CON0_DISP_OVL0 |
+				  CG_CON0_DISP_OVL0_2L |
+				  CG_CON0_DISP_RDMA0 |
+				  CG_CON0_DISP_COLOR0 |
+				  CG_CON0_DISP_CCORR0 |
+				  CG_CON0_DISP_AAL0 |
+				  CG_CON0_DISP_DITHER0 |
+				  CG_CON0_DISP_GAMMA0,
+	CG_CON0_ALL	    	= 0xffffffff
+};
+
+/* DISP_REG_CONFIG_MMSYS_CG_CON1
+   Configures free-run clock gating 1
+	0: Enable clock
+	1: Clock gating */
+enum {
+	CG_CON1_DISP_DSI0		= BIT(0),
+	CG_CON1_DISP_DSI0_INTERFACE	= BIT(1),
+	CG_CON1_DISP_26M		= BIT(7),
+
+	CG_CON1_ALL	      = 0xffffffff
+};
+
+enum {
+	OVL0_MOUT_EN_RDMA0 		= BIT(0),
+	OVL0_MOUT_EN_OVL0_2L 		= BIT(4),
+	OVL0_2L_MOUT_EN_DISP_PATH0    	= BIT(0),
+	OVL1_2L_MOUT_EN_DISP_RDMA1 	= BIT(4),
+	DITHER0_MOUT_EN_DISP_DSI0	= BIT(0),
+};
+
+enum {
+	DISP_PATH0_SEL_IN_OVL0     = 0,
+	DISP_PATH0_SEL_IN_OVL0_2L  = 1,
+	DSI0_SEL_IN_DITHER0_MOUT   = 0,
+	DSI0_SEL_IN_RDMA0	   = 1,
+	RDMA0_SOUT_SEL_IN_DSI0	   = 0,
+	RDMA0_SOUT_SEL_IN_COLOR    = 1,
+};
+
+struct disp_mutex_regs {
+	u32 inten;
+	u32 intsta;
+	u32 reserved0[6];
+	struct {
+		u32 en;
+		u32 dummy;
+		u32 rst;
+		u32 ctl;
+		u32 mod;
+		u32 reserved[3];
+	} mutex[12];
+};
+
+static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE;
+
+enum {
+	MUTEX_MOD_DISP_RDMA0	= BIT(0),
+	MUTEX_MOD_DISP_RDMA1	= BIT(1),
+	MUTEX_MOD_DISP_OVL0	= BIT(9),
+	MUTEX_MOD_DISP_OVL0_2L	= BIT(10),
+	MUTEX_MOD_DISP_OVL1_2L	= BIT(11),
+	MUTEX_MOD_DISP_WDMA0	= BIT(12),
+	MUTEX_MOD_DISP_COLOR0	= BIT(13),
+	MUTEX_MOD_DISP_CCORR0	= BIT(14),
+	MUTEX_MOD_DISP_AAL0	= BIT(15),
+	MUTEX_MOD_DISP_GAMMA0	= BIT(16),
+	MUTEX_MOD_DISP_DITHER0	= BIT(17),
+	MUTEX_MOD_DISP_PWM0	= BIT(28),
+	MUTEX_MOD_MAIN_PATH	= MUTEX_MOD_DISP_OVL0 | MUTEX_MOD_DISP_OVL0_2L |
+				  MUTEX_MOD_DISP_RDMA0 | MUTEX_MOD_DISP_COLOR0 |
+				  MUTEX_MOD_DISP_CCORR0 | MUTEX_MOD_DISP_AAL0 |
+				  MUTEX_MOD_DISP_GAMMA0| MUTEX_MOD_DISP_DITHER0,
+};
+
+enum {
+	MUTEX_SOF_SINGLE_MODE = 0,
+	MUTEX_SOF_DSI0 = 1,
+	MUTEX_SOF_DPI0 = 2,
+};
+
+struct disp_ovl_regs {
+	u32 sta;
+	u32 inten;
+	u32 intsta;
+	u32 en;
+	u32 trig;
+	u32 rst;
+	u32 reserved_0x018[2];
+	u32 roi_size;
+	u32 datapath_con;
+	u32 roi_bgclr;
+	u32 src_con;
+	struct {
+		u32 con;
+		u32 srckey;
+		u32 src_size;
+		u32 offset;
+		u32 reserved0;
+		u32 pitch;
+		u32 reserved1[2];
+	} layer[4];
+	u32 reserved_0x0B0[4];
+	struct {
+		u32 ctrl;
+		u32 reserved0;
+		u32 mem_gmc_setting;
+		u32 mem_slow_con;
+		u32 fifo_ctrl;
+		u32 reserved1[3];
+	} rdma[4];
+	u32 reserved_0x140[880];
+	u32 reserved_0xF00[16];
+	u32 l0_addr;
+	u32 reserved_0xF44[7];
+	u32 l1_addr;
+	u32 reserved_0xF64[7];
+	u32 l2_addr;
+	u32 reserved_0xF84[7];
+	u32 l3_addr;
+};
+
+check_member(disp_ovl_regs, reserved_0x018, 0x018);
+check_member(disp_ovl_regs, roi_size, 0x020);
+check_member(disp_ovl_regs, reserved_0x0B0, 0x0B0);
+check_member(disp_ovl_regs, reserved_0x140, 0x140);
+check_member(disp_ovl_regs, reserved_0xF00, 0xF00);
+check_member(disp_ovl_regs, l0_addr, 0xF40);
+check_member(disp_ovl_regs, l3_addr, 0xFA0);
+static struct disp_ovl_regs *const disp_ovl[2] = {
+	(void *)DISP_OVL0_BASE, (void *)DISP_OVL0_2L_BASE
+};
+
+struct disp_rdma_regs {
+	u32 int_enable;
+	u32 int_status;
+	u32 reserved0[2];
+	u32 global_con;
+	u32 size_con_0;
+	u32 size_con_1;
+	u32 target_line;
+	u32 reserved1;
+	u32 mem_con;
+	u32 reserved2;
+	u32 mem_src_pitch;
+	u32 mem_gmc_setting_0;
+	u32 mem_gmc_setting_1;
+	u32 mem_slow_con;
+	u32 mem_gmc_setting_2;
+	u32 fifo_con;
+	u32 reserved3[4];
+	u32 cf[3][3];
+	u32 cf_pre_add[3];
+	u32 cf_post_add[3];
+	u32 dummy;
+	u32 debug_out_sel;
+};
+
+enum {
+	RDMA_ENGINE_EN		= BIT(0),
+	RDMA_FIFO_UNDERFLOW_EN	= BIT(31),
+	RDMA_FIFO_SIZE_0 = 5, /* 5K */
+	RDMA_VREFRESH = 60, /* vrefresh 60HZ */
+	RDMA_MEM_GMC = 0x40402020,
+};
+
+check_member(disp_rdma_regs, debug_out_sel, 0x94);
+static struct disp_rdma_regs *const disp_rdma[2] = {
+	(void *)DISP_RDMA0_BASE,
+	(void *)DISP_RDMA1_BASE,
+};
+
+struct disp_color_regs {
+	u8 reserved0[1024];
+	u32 cfg_main;
+	u8 reserved1[2044];
+	u32 start;
+	u8 reserved2[76];
+	u32 width;
+	u32 height;
+};
+
+check_member(disp_color_regs, cfg_main, 0x400);
+check_member(disp_color_regs, start, 0xC00);
+check_member(disp_color_regs, width, 0xC50);
+check_member(disp_color_regs, height, 0xC54);
+static struct disp_color_regs *const disp_color = (void *)DISP_COLOR0_BASE;
+
+enum {
+	COLOR_BYPASS_ALL = BIT(7),
+	COLOR_SEQ_SEL    = BIT(13),
+};
+
+struct disp_pq_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 status;
+	u32 reserved0[3];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+};
+
+enum {
+	PQ_EN 		= BIT(0),
+	PQ_RELAY_MODE    	= BIT(0),
+};
+
+static struct disp_pq_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE;
+
+static struct disp_pq_regs *const disp_aal = (void *)DISP_AAL0_BASE;
+
+static struct disp_pq_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE;
+
+static struct disp_pq_regs *const disp_dither = (void *)DISP_DITHER0_BASE;
+
+enum OVL_INPUT_FORMAT {
+	OVL_INFMT_RGB565 = 0,
+	OVL_INFMT_RGB888 = 1,
+	OVL_INFMT_RGBA8888 = 2,
+	OVL_INFMT_ARGB8888 = 3,
+	OVL_INFMT_UYVY = 4,
+	OVL_INFMT_YUYV = 5,
+	OVL_INFMT_UNKNOWN = 16,
+
+	OVL_COLOR_BASE = 30,
+	OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE,
+	OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE,
+	OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE,
+	OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE,
+};
+
+void mtk_ddp_init(void);
+void mtk_ddp_mode_set(const struct edid *edid);
+
+#endif
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic4aecc58d081f14f5d136b9ff8e813e6f40f78eb
Gerrit-Change-Number: 31478
Gerrit-PatchSet: 1
Gerrit-Owner: yongqiang niu yongqiang.niu@mediatek.com
Gerrit-MessageType: newchange



    

Change in ...coreboot[master]: mediatek/mt8183: Add display driver