[XS] Change in coreboot[main]: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default

[Felix Held (Code Review)]

Attention is currently required from: Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier, Maximilian Brune.

Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86272?usp=email )

Change subject: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default
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Patch Set 3: Code-Review+2

(2 comments)

File src/soc/amd/cezanne/chipset.cb:

https://review.coreboot.org/c/coreboot/+/86272/comment/8060ee02_1455f999?usp... :
PS2, Line 90: xgbe_0
> is xgbe_0 and xgbe_1 always disabled by FSP?

the two xgbe controllers can't be used on the silicon this was originally tested with, so i'd guess that they just can't show up showed up in that case. if some out of tree board uses those, it needs to make sure to enable them. this patch is about the bridges though. if we end up adding upds for this, that's something for another patch

https://review.coreboot.org/c/coreboot/+/86272/comment/51aa5f73_7d634ca0?usp... :
PS2, Line 96: i2s_ac97
> is i2s_ac97 always disabled by FSP?

uh, that's a good question to which i don't know the answer. i'd say that it'll probably be fine to have it disabled here