[M] Change in coreboot[main]: ec/google/chromeec: Publish LPC GMR address range via CREC _CRS

[Subrata Banik (Code Review)]

Attention is currently required from: Boris Mittelberg, Gwendal Grignou, Subrata Banik.

Hello Boris Mittelberg, Caveh Jalali, Gwendal Grignou, Kapil Porwal, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85603?usp=email

to look at the new patch set (#3).

Change subject: ec/google/chromeec: Publish LPC GMR address range via CREC _CRS
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ec/google/chromeec: Publish LPC GMR address range via CREC _CRS

This change allows the Chrome EC (CREC) ACPI device to publish the LPC
Generic Memory Range (GMR) address range using the _CRS method.

The Google CREC driver can now parse this information to determine the
MMIO address map, enabling access to the LPC GMR register space.

This addresses the issue where the CREC driver was unable to
automatically determine the LPC GMR base address.

TEST=Able to build and boot google/brox.

without this patch:

brox-rev0 ~ # cat /proc/iomem | grep fe0

fe000000-fe00ffff : INTC1026:00
fe000000-fe00ffff : intel_scu_ipc
fe03e000-fe03efff : 0000:00:1e.0
fe03e000-fe03e1ff : lpss_dev
fe03e000-fe03e1ff : serial
fe03e200-fe03e2ff : lpss_priv
fe03e800-fe03efff : idma64.4
fe03e800-fe03efff : idma64.4 idma64.4

with this patch:

brox-rev0 ~ # cat /proc/iomem | grep fe0
fe000000-fe00ffff : INTC1026:00
fe000000-fe00ffff : intel_scu_ipc
fe03e000-fe03efff : 0000:00:1e.0
fe03e000-fe03e1ff : lpss_dev
fe03e000-fe03e1ff : serial
fe03e200-fe03e2ff : lpss_priv
fe03e800-fe03efff : idma64.4
fe03e800-fe03efff : idma64.4 idma64.4
fe0b0000-fe0bffff : GOOG0004:00

Change-Id: Ib3ea3e2a482f9eceaa8c15e38b7e708b156bc978
Signed-off-by: Subrata Banik 
---
M src/ec/google/chromeec/Kconfig
M src/ec/google/chromeec/acpi/cros_ec.asl
2 files changed, 35 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/85603/3