Change in coreboot[master]: cpu/intel/msr.h: Sort MSRs in ascending order

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55457 )

Change subject: cpu/intel/msr.h: Sort MSRs in ascending order
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cpu/intel/msr.h: Sort MSRs in ascending order

Sort MSR definitions in ascending order to keep things organized.

Change-Id: Iadfd28014dc6f41dae7b52b1550c699c89fe8bdc
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55457
Tested-by: build bot (Jenkins) 
Reviewed-by: Michael Niewöhner 
---
M src/include/cpu/intel/msr.h
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h
index 9d2b62f..097ddb6 100644
--- a/src/include/cpu/intel/msr.h
+++ b/src/include/cpu/intel/msr.h
@@ -7,10 +7,6 @@
  * Common MSRs for Intel CPUs
  */

-#define MSR_FEATURE_CONFIG	0x13c
-#define  AESNI_DISABLE		(1 << 1)
-#define  AESNI_LOCK		(1 << 0)
-
 #define MSR_PIC_MSG_CONTROL	0x2e
 #define  TPR_UPDATES_DISABLE	(1 << 10)

@@ -26,6 +22,10 @@
 #define  B_BOOT_GUARD_SACM_INFO_BTG_CAPABILITY	(1ull << 32)
 #define  B_BOOT_GUARD_SACM_INFO_TXT_CAPABILITY	(1ull << 34)

+#define MSR_FEATURE_CONFIG	0x13c
+#define  AESNI_DISABLE		(1 << 1)
+#define  AESNI_LOCK		(1 << 0)
+
 #define MSR_PKG_C10_RESIDENCY	0x632

#endif /* CPU_INTEL_MSR_H */