Change in coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock

[Patrick Georgi (Code Review)]

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Michal Motyl.
Patrick Georgi has uploaded a new patch set (#23) to the change originally created by Julien Viard de Galbert. ( https://review.coreboot.org/c/coreboot/+/25442 )

Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
......................................................................

soc/intel/denverton_ns: Implement PCIe post config + lock

- Configure PCIe maximum payload size to fix Intel SSD
- Lock Down PCIe Configuration

Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Signed-off-by: Julien Viard de Galbert 
---
M src/soc/intel/denverton_ns/lpc.c
1 file changed, 35 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/25442/23