Change in coreboot[master]: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute

[huayang duan (Code Review)]

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
......................................................................

soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute

the delay cell result should using the ddr clock pll rate for compute,
should not div 2 more.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Signed-off-by: Huayang Duan

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
---
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
1 file changed, 14 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36990/1

diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
index 1dc1ca5..c61e237 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
@@ -1588,18 +1588,24 @@
    struct per_byte_dly center_dly[DQS_NUMBER];
    u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH];

+
+	/*
+	* The clock rate should be (data rate/2 - 4),
+	* and the 4MHz is introduced to reduce interference from
+	* RF peripherals like modem, WiFi, BlueTooth.
+	*/
    switch (freq_group) {
    case LP4X_DDR1600:
-		clock_rate = 800;
+		clock_rate = 796;
    	break;
    case LP4X_DDR2400:
-		clock_rate = 1200;
+		clock_rate = 1196;
    	break;
    case LP4X_DDR3200:
-		clock_rate = 1600;
+		clock_rate = 1596;
    	break;
    case LP4X_DDR3600:
-		clock_rate = 1866;
+		clock_rate = 1792;
    	break;
    default:
    	die("Invalid DDR frequency group %u\n", freq_group);
@@ -1612,7 +1618,7 @@
    	use_delay_cell = 0;

if (fast_calib && bypass_tx) {
-		dramc_dbg("bypass TX\n");
+		dramc_dbg("bypass TX, clock_rate:%d\n", clock_rate);
    	for (u8 byte = 0; byte < DQS_NUMBER; byte++) {
    		center_dly[byte].min_center = params->tx_center_min[chn][rank][byte];
    		center_dly[byte].max_center = params->tx_center_max[chn][rank][byte];
@@ -1645,8 +1651,10 @@
    			tune_diff = vref_dly[index].win_center -
    				center_dly[byte].min_center;
    			dq_delay_cell[index] = ((tune_diff * 100000000) /
-					(clock_rate / 2 * 64)) / dly_cell_unit;
+					(clock_rate * 64)) / dly_cell_unit;
    			byte_dly_cell[byte] |= (dq_delay_cell[index] << (bit * 4));
+				dramc_show("u1DelayCellOfst[%d]=%d cells (%d PI)\n",
+					index, dq_delay_cell[index], tune_diff);
    		}
    	}
    }

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
......................................................................

Patch Set 1: Code-Review+1

(7 comments)

https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@7 
PS1, Line 7:  Tx delay cell should use ddr clock do compute
Use DDR clock to compute Tx delay cell

https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 
PS1, Line 9: using
use

https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 
PS1, Line 9: compute
computation

https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 
PS1, Line 9: the
The

https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 
PS1, Line 9: ddr clock pll
DDR clock PLL

https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@10 
PS1, Line 10: should not div 2 more.
and should not be divided by 2.

https://review.coreboot.org/c/coreboot/+/36990/1/src/soc/mediatek/mt8183/dra... 
File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:

https://review.coreboot.org/c/coreboot/+/36990/1/src/soc/mediatek/mt8183/dra... 
PS1, Line 1595:  
and Bluetooth.

[huayang duan (Code Review)]

Hello Julius Werner, Hung-Te Lin, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36990

to look at the new patch set (#2).

Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
......................................................................

soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute

the delay cell result should using the ddr clock pll rate for compute,
should not div 2 more.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Signed-off-by: Huayang Duan

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
---
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
1 file changed, 14 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36990/2

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
......................................................................

Patch Set 2: Code-Review+2

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
......................................................................

Patch Set 2: Code-Review+1

Please correct the description and comments.

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... 
File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:

https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... 
PS2, Line 1608: 1792
@huayang, why is this 1792? The delta is more than other (8), also it's too different from original value (1866->1800-4)

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... 
File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:

https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... 
PS2, Line 1599: 796
I wonder if it'll be more clear if we do

const clock_rate_delta = 4; /* 4MHz to reduce interference from RF peripherals like modem, WiFi, Bluetooth */

switch (freq_group) {
 case LP4X_DDR1600:
   clock_rate = 1600 / 2 - clock_rate_delta;
   break;

case LP4X_DDR2400:
   clock_rate = 2400 / 2 - clock_rate_delta;

...

[huayang duan (Code Review)]

huayang duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... 
File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:

https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... 
PS2, Line 1608: 1792
> @huayang, why is this 1792? The delta is more than other (8), also it's too different from original  […]

the real clock DRAM control using is 796, 1596 and 1792 for avoid other RF device.

Dram Type= 6, Freq= 796, FreqGroup= 800, CH_0, rank 0
Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
Dram Type= 6, Freq= 1792, FreqGroup= 1866, CH_0, rank 0

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
......................................................................

Patch Set 2:

(3 comments)

https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... 
File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:

https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... 
PS2, Line 1593: The clock rate should be (data rate/2 - 4),
              : 	* and the 4MHz is introduced to reduce interference from
              : 	* RF peripherals like modem, WiFi, BlueTooth.
can you revise this to

The clock rate is usually (data rate/2 - 4),
and the 4MHz is introduced to reduce interference from
RF peripherals like modem, WiFi, BlueTooth.
For some higher frequency the number may be different.

https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... 
PS2, Line 1599: 796
> I wonder if it'll be more clear if we do […]

Ack

https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... 
PS2, Line 1608: 1792
> the real clock DRAM control using is 796, 1596 and 1792 for avoid other RF device. […]

Ack

[huayang duan (Code Review)]

Hello Yu-Ping Wu, Julius Werner, Hung-Te Lin, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36990

to look at the new patch set (#3).

Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
......................................................................

soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute

the delay cell result should using the ddr clock pll rate for compute,
should not div 2 more.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Signed-off-by: Huayang Duan

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
---
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
1 file changed, 13 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36990/3

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
......................................................................

Patch Set 3: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... 
File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:

https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... 
PS2, Line 1593: The clock rate should be (data rate/2 - 4),
              : 	* and the 4MHz is introduced to reduce interference from
              : 	* RF peripherals like modem, WiFi, BlueTooth.
> can you revise this to […]

Ack

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has uploaded a new patch set (#4) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

The delay cell result should use DDR clock PLL rate for computation,
and should not be divided by 2.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Signed-off-by: Huayang Duan

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
---
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
1 file changed, 13 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36990/4

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

Patch Set 4:

(6 comments)

https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@7 
PS1, Line 7:  Tx delay cell should use ddr clock do compute
> Use DDR clock to compute Tx delay cell

Done

https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 
PS1, Line 9: compute
> computation

Done

https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 
PS1, Line 9: the
> The

Done

https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 
PS1, Line 9: using
> use

Done

https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 
PS1, Line 9: ddr clock pll
> DDR clock PLL

Done

https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@10 
PS1, Line 10: should not div 2 more.
> and should not be divided by 2.

Done

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36990/1/src/soc/mediatek/mt8183/dra... 
File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:

https://review.coreboot.org/c/coreboot/+/36990/1/src/soc/mediatek/mt8183/dra... 
PS1, Line 1595:
> and Bluetooth.

Done

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/36990/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36990/4//COMMIT_MSG@15 
PS4, Line 15: Signed-off-by: Huayang Duan 
Move this line below Change-Id.

https://review.coreboot.org/c/coreboot/+/36990/4/src/soc/mediatek/mt8183/dra... 
File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:

https://review.coreboot.org/c/coreboot/+/36990/4/src/soc/mediatek/mt8183/dra... 
PS4, Line 1593: for
to

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

Patch Set 4: Code-Review+1

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36990/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36990/4//COMMIT_MSG@11 
PS4, Line 11: 
What problem does this fix?

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has uploaded a new patch set (#5) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

The delay cell result should use DDR clock PLL rate for computation,
and should not be divided by 2.
This helps improving DRAM stability.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Signed-off-by: Huayang Duan

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
---
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
1 file changed, 13 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36990/5

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has uploaded a new patch set (#6) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

The delay cell result should use DDR clock PLL rate for computation,
and should not be divided by 2.
This helps improving DRAM stability.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
Signed-off-by: Huayang Duan 
---
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
1 file changed, 13 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36990/6

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

Patch Set 6:

(2 comments)

https://review.coreboot.org/c/coreboot/+/36990/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36990/4//COMMIT_MSG@11 
PS4, Line 11:
> What problem does this fix?

Improved DRAM stability.

https://review.coreboot.org/c/coreboot/+/36990/4//COMMIT_MSG@15 
PS4, Line 15: Signed-off-by: Huayang Duan
> Move this line below Change-Id.

Done

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has uploaded a new patch set (#7) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

The delay cell result should use DDR clock PLL rate for computation,
and should not be divided by 2.
This helps improving DRAM stability.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
Signed-off-by: Huayang Duan 
---
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
1 file changed, 14 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36990/7

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36990/4/src/soc/mediatek/mt8183/dra... 
File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:

https://review.coreboot.org/c/coreboot/+/36990/4/src/soc/mediatek/mt8183/dra... 
PS4, Line 1593: for
> to

Done

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

Patch Set 7: Code-Review+1

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

Patch Set 7:

(3 comments)

https://review.coreboot.org/c/coreboot/+/36990/7//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36990/7//COMMIT_MSG@11 
PS7, Line 11: helps improving
helps to improve

https://review.coreboot.org/c/coreboot/+/36990/7/src/soc/mediatek/mt8183/dra... 
File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:

https://review.coreboot.org/c/coreboot/+/36990/7/src/soc/mediatek/mt8183/dra... 
PS7, Line 1608: 		clock_rate = 1792;
So delta = 4, but for 3600 where it is 8? Are these values documented in some datasheet?

https://review.coreboot.org/c/coreboot/+/36990/7/src/soc/mediatek/mt8183/dra... 
PS7, Line 1621: 		dramc_dbg("bypass TX, clock_rate:%d\n", clock_rate);
Please add a space after the colon.

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has uploaded a new patch set (#8) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

The delay cell result should use DDR clock PLL rate for computation,
and should not be divided by 2.
This helps to improve DRAM stability.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
Signed-off-by: Huayang Duan 
---
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
1 file changed, 14 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36990/8

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

Patch Set 8:

(3 comments)

https://review.coreboot.org/c/coreboot/+/36990/7//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36990/7//COMMIT_MSG@11 
PS7, Line 11: helps improving
> helps to improve

Done

https://review.coreboot.org/c/coreboot/+/36990/7/src/soc/mediatek/mt8183/dra... 
File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:

https://review.coreboot.org/c/coreboot/+/36990/7/src/soc/mediatek/mt8183/dra... 
PS7, Line 1608: 		clock_rate = 1792;
> So delta = 4, but for 3600 where it is 8? Are these values documented in some datasheet?

According to MTK this is something trained by practice and just hard-coded.
And yes it's 8 for 3600.

https://review.coreboot.org/c/coreboot/+/36990/7/src/soc/mediatek/mt8183/dra... 
PS7, Line 1621: 		dramc_dbg("bypass TX, clock_rate:%d\n", clock_rate);
> Please add a space after the colon.

Done

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has uploaded a new patch set (#9) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

The delay cell result should use DDR clock PLL rate for computation,
and should not be divided by 2.
This helps to improve DRAM stability.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
Signed-off-by: Huayang Duan 
---
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
1 file changed, 14 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36990/9

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

Patch Set 9: Code-Review+1

any other concerns?

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

Patch Set 9: Code-Review+2

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

Patch Set 9: Code-Review+2

Change in coreboot[master]: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
......................................................................

soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell

The delay cell result should use DDR clock PLL rate for computation,
and should not be divided by 2.
This helps to improve DRAM stability.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
Signed-off-by: Huayang Duan 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36990
Tested-by: build bot (Jenkins) 
Reviewed-by: Hung-Te Lin 
Reviewed-by: Patrick Georgi 
---
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
1 file changed, 14 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved
  Hung-Te Lin: Looks good to me, approved

diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
index 8c17d84..0ec0193 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
@@ -1588,18 +1588,24 @@
    struct per_byte_dly center_dly[DQS_NUMBER];
    u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH];

+
+	/*
+	 * The clock rate is usually (frequency / 2 - delta), where the delta
+	 * is introduced to avoid interference from RF peripherals like
+	 * modem, WiFi, and Bluetooth.
+	 */
    switch (freq_group) {
    case LP4X_DDR1600:
-		clock_rate = 800;
+		clock_rate = 796;
    	break;
    case LP4X_DDR2400:
-		clock_rate = 1200;
+		clock_rate = 1196;
    	break;
    case LP4X_DDR3200:
-		clock_rate = 1600;
+		clock_rate = 1596;
    	break;
    case LP4X_DDR3600:
-		clock_rate = 1866;
+		clock_rate = 1792;
    	break;
    default:
    	die("Invalid DDR frequency group %u\n", freq_group);
@@ -1612,7 +1618,7 @@
    	use_delay_cell = 0;

if (fast_calib && bypass_tx) {
-		dramc_dbg("bypass TX\n");
+		dramc_dbg("bypass TX, clock_rate: %d\n", clock_rate);
    	for (u8 byte = 0; byte < DQS_NUMBER; byte++) {
    		center_dly[byte].min_center = params->tx_center_min[chn][rank][byte];
    		center_dly[byte].max_center = params->tx_center_max[chn][rank][byte];
@@ -1645,8 +1651,10 @@
    			tune_diff = vref_dly[index].win_center -
    				center_dly[byte].min_center;
    			dq_delay_cell[index] = ((tune_diff * 100000000) /
-					(clock_rate / 2 * 64)) / dly_cell_unit;
+					(clock_rate * 64)) / dly_cell_unit;
    			byte_dly_cell[byte] |= (dq_delay_cell[index] << (bit * 4));
+				dramc_show("u1DelayCellOfst[%d]=%d cells (%d PI)\n",
+					index, dq_delay_cell[index], tune_diff);
    		}
    	}
    }