Change in coreboot[master]: mb/intel/adlrvp_m: Configure DP_HPD as PAD_NC and disable DdiPortHpd

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55548 )

Change subject: mb/intel/adlrvp_m: Configure DP_HPD as PAD_NC and disable DdiPortHpd
......................................................................

mb/intel/adlrvp_m: Configure DP_HPD as PAD_NC and disable DdiPortHpd

GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1), this causes redundancy with legacy HPD interruption.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.

BUG=None
TEST=Boot to kernel and verified no kernel HPD pins assertion message.

Signed-off-by: Bernardo Perez Priego 
Change-Id: I80ef40a1aca19cd6ad56219175d2fd40890a393d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55548
Tested-by: build bot (Jenkins) 
Reviewed-by: Sanrio Alvares 
Reviewed-by: Bora Guvendik 
---
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/adlrvp/gpio_m.c
2 files changed, 7 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Bora Guvendik: Looks good to me, approved
  Sanrio Alvares: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index ae24842..4d32ce9 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -86,6 +86,10 @@
    	[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
    }"

+	# Disable DDI ports HPD
+	register "DdiPort1Hpd" = "0"
+	register "DdiPort2Hpd" = "0"
+
    # TCSS USB3
    register "TcssAuxOri" = "0"

diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c
index 6f89fd2..d5eeffa 100644
--- a/src/mainboard/intel/adlrvp/gpio_m.c
+++ b/src/mainboard/intel/adlrvp/gpio_m.c
@@ -110,7 +110,9 @@
    /* HPD_1 (E14) and HPD_2 (A18) pins */
    PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
    PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
+
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),

/* GPIO pin for PCIE SRCCLKREQB */
    PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),