Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41931 )
Change subject: cpu/intel/broadwell: Add Kconfig ......................................................................
cpu/intel/broadwell: Add Kconfig
Move the CPU-related Kconfig settings from soc to the cpu scope.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: I6f65f300dd212bb812f1db5d9813ec57cf1d7cfb Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc A src/cpu/intel/broadwell/Kconfig M src/soc/intel/broadwell/Kconfig 4 files changed, 43 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/41931/1
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 43b360b..b609422 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -14,6 +14,7 @@ source "src/cpu/intel/model_f3x/Kconfig" source "src/cpu/intel/model_f4x/Kconfig" source "src/cpu/intel/haswell/Kconfig" +source "src/cpu/intel/broadwell/Kconfig" # Sockets/Slots source "src/cpu/intel/slot_1/Kconfig" source "src/cpu/intel/socket_BGA956/Kconfig" diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 21dc291..95e4b11 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -13,7 +13,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell -subdirs-$(CONFIG_SOC_INTEL_BROADWELL) += broadwell +subdirs-$(CONFIG_CPU_INTEL_BROADWELL) += broadwell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775
diff --git a/src/cpu/intel/broadwell/Kconfig b/src/cpu/intel/broadwell/Kconfig new file mode 100644 index 0000000..5889646 --- /dev/null +++ b/src/cpu/intel/broadwell/Kconfig @@ -0,0 +1,40 @@ +config CPU_INTEL_BROADWELL + bool + help + Intel Broadwell and Haswell ULT CPU support. + +if CPU_INTEL_BROADWELL + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select CPU_INTEL_COMMON + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select NO_FIXED_XIP_ROM_SIZE + select PARALLEL_MP + select SMP + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CPU + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_MONOTONIC_TIMER + select TSC_SYNC_MFENCE + select UDELAY_TSC + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config IED_REGION_SIZE + hex + default 0x400000 + +config SMM_RESERVED_SIZE + hex + default 0x100000 + +endif diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index bdbdda4..2048d97 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -8,14 +8,9 @@ config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_INTEL_BROADWELL select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select HAVE_SMI_HANDLER @@ -25,14 +20,10 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_GMA_ACPI select MRC_SETTINGS_PROTECT - select NO_FIXED_XIP_ROM_SIZE - select PARALLEL_MP select REG_SCRIPT select RTC - select SMP select SOC_INTEL_COMMON select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOUTHBRIDGE_INTEL_COMMON_RESET @@ -40,11 +31,6 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SPI_FLASH - select SSE2 - select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE - select UDELAY_TSC
config PCIEXP_ASPM bool @@ -90,18 +76,6 @@ hex default 0xf0000000
-config SMM_TSEG_SIZE - hex - default 0x800000 - -config IED_REGION_SIZE - hex - default 0x400000 - -config SMM_RESERVED_SIZE - hex - default 0x100000 - config VGA_BIOS_ID string default "8086,0406"
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41931
to look at the new patch set (#5).
Change subject: cpu/intel/broadwell: Add Kconfig ......................................................................
cpu/intel/broadwell: Add Kconfig
Move the CPU-related Kconfig settings from soc to the cpu scope.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: I6f65f300dd212bb812f1db5d9813ec57cf1d7cfb Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc A src/cpu/intel/broadwell/Kconfig M src/soc/intel/broadwell/Kconfig 4 files changed, 42 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/41931/5
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41931
to look at the new patch set (#9).
Change subject: cpu/intel/broadwell: Add Kconfig ......................................................................
cpu/intel/broadwell: Add Kconfig
Move the CPU-related Kconfig settings from soc to the cpu scope.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: I6f65f300dd212bb812f1db5d9813ec57cf1d7cfb Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc A src/cpu/intel/broadwell/Kconfig M src/soc/intel/broadwell/Kconfig 4 files changed, 42 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/41931/9
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41931
to look at the new patch set (#12).
Change subject: cpu/intel/broadwell: Add Kconfig ......................................................................
cpu/intel/broadwell: Add Kconfig
Move the CPU-related Kconfig settings from soc to the cpu scope.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: I6f65f300dd212bb812f1db5d9813ec57cf1d7cfb Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc A src/cpu/intel/broadwell/Kconfig M src/soc/intel/broadwell/Kconfig 4 files changed, 42 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/41931/12
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41931 )
Change subject: cpu/intel/broadwell: Add Kconfig ......................................................................
Abandoned
-
Angel Pons (Code Review)