Change in coreboot[master]: soc/intel/cannonlake: Use set_dev_state_by_devicetree()

[Felix Singer (Code Review)]

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52835 )

Change subject: soc/intel/cannonlake: Use set_dev_state_by_devicetree()
......................................................................

soc/intel/cannonlake: Use set_dev_state_by_devicetree()

Change-Id: If5fed7d37676458354b24b8426cf8e77f32292ab
Signed-off-by: Felix Singer 
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 50 insertions(+), 89 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/52835/1

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index d7772f1..4f6c8e0 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -3,6 +3,7 @@
 #include <bootsplash.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <device/devenmap.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
@@ -136,6 +137,26 @@

mainboard_silicon_init_params(supd);

+	const struct device_enable_map devmap[] = {
+		{ &params->SataEnable,		PCH_DEVFN_SATA },
+		{ &params->PchLanEnable,	PCH_DEVFN_GBE },
+		{ &params->XdciEnable,		PCH_DEVFN_USBOTG },
+		{ &params->ScsEmmcEnabled,	PCH_DEVFN_EMMC },
+		{ &params->ScsUfsEnabled,	PCH_DEVFN_UFS },
+		{ &params->ScsSdCardEnabled,	PCH_DEVFN_SDCARD },
+		{ &params->Device4Enable,	SA_DEVFN_DSP },
+#if CONFIG(SOC_INTEL_COMETLAKE)
+		{ &params->CnviMode,		PCH_DEVFN_CNViWIFI },
+#else
+		{ &params->PchCnviMode,		PCH_DEVFN_CNViWIFI },
+#endif
+#if !CONFIG(HECI_DISABLE_USING_SMM)
+		{ &params->Heci1Disabled,	PCH_DEVFN_CSE,	1 },
+#endif
+	};
+
+	set_dev_state_by_devicetree(devmap, ARRAY_SIZE(devmap));
+
    const struct soc_power_limits_config *soc_config;
    soc_config = &config->power_limits_config;
    /* Set PsysPmax if it is available from DT */
@@ -149,11 +170,7 @@
    params->PchLockDownRtcMemoryLock = 0;

/* SATA */
-	dev = pcidev_path_on_root(PCH_DEVFN_SATA);
-	if (!dev)
-		params->SataEnable = 0;
-	else {
-		params->SataEnable = dev->enabled;
+	if (params->SataEnable) {
    	params->SataMode = config->SataMode;
    	params->SataPwrOptEnable = config->satapwroptimize;
    	params->SataSalpSupport = config->SataSalpSupport;
@@ -175,25 +192,19 @@
    params->PchPmSlpS0Vm075VSupport = config->PchPmSlpS0Vm075VSupport;

/* Lan */
-	dev = pcidev_path_on_root(PCH_DEVFN_GBE);
-	if (!dev)
-		params->PchLanEnable = 0;
-	else {
-		params->PchLanEnable = dev->enabled;
-		if (config->s0ix_enable && params->PchLanEnable) {
-			/*
-			 * The VmControl UPDs need to be set as per board
-			 * design to allow voltage margining in S0ix to lower
-			 * power consumption.
-			 * But if GbE is enabled, voltage magining cannot be
-			 * enabled, so the Vm control UPDs need to be set to 0.
-			 */
-			params->SlpS0WithGbeSupport = 1;
-			params->PchPmSlpS0VmRuntimeControl = 0;
-			params->PchPmSlpS0Vm070VSupport = 0;
-			params->PchPmSlpS0Vm075VSupport = 0;
-			ignore_gbe_ltr();
-		}
+	if (params->PchLanEnable && config->s0ix_enable) {
+		/*
+		 * The VmControl UPDs need to be set as per board
+		 * design to allow voltage margining in S0ix to lower
+		 * power consumption.
+		 * But if GbE is enabled, voltage magining cannot be
+		 * enabled, so the Vm control UPDs need to be set to 0.
+		 */
+		params->SlpS0WithGbeSupport = 1;
+		params->PchPmSlpS0VmRuntimeControl = 0;
+		params->PchPmSlpS0Vm070VSupport = 0;
+		params->PchPmSlpS0Vm075VSupport = 0;
+		ignore_gbe_ltr();
    }

/* Audio */
@@ -310,12 +321,9 @@

/* Enable xDCI controller if enabled in devicetree and allowed */
    dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
-	if (dev) {
-		if (!xdci_can_enable())
-			dev->enabled = 0;
-		params->XdciEnable = dev->enabled;
-	} else
+	if (!xdci_can_enable()) {
    	params->XdciEnable = 0;
+	}

/* Set Debug serial port */
    params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
@@ -323,19 +331,6 @@
    params->SerialIoEnableDebugUartAfterPost = CONFIG(INTEL_LPSS_UART_FOR_CONSOLE);
 #endif

-	/* Enable CNVi Wifi if enabled in device tree */
-	dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI);
-#if CONFIG(SOC_INTEL_COMETLAKE)
-	if (dev)
-		params->CnviMode = dev->enabled;
-	else
-		params->CnviMode = 0;
-#else
-	if (dev)
-		params->PchCnviMode = dev->enabled;
-	else
-		params->PchCnviMode = 0;
-#endif
    /* PCI Express */
    for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
    	if (config->PcieClkSrcUsage[i] == 0)
@@ -366,11 +361,7 @@
    };

/* eMMC and SD */
-	dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
-	if (!dev)
-		params->ScsEmmcEnabled = 0;
-	else {
-		params->ScsEmmcEnabled = dev->enabled;
+	if (params->ScsEmmcEnabled) {
    	params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
    	params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
    	if (config->EmmcHs400DllNeed == 1) {
@@ -381,11 +372,7 @@
    	}
    }

-	dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
-	if (!dev) {
-		params->ScsSdCardEnabled = 0;
-	} else {
-		params->ScsSdCardEnabled = dev->enabled;
+	if (params->ScsSdCardEnabled) {
    	params->SdCardPowerEnableActiveHigh =
    		CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
 #if CONFIG(SOC_INTEL_COMETLAKE)
@@ -393,18 +380,9 @@
 #endif
    }

-	dev = pcidev_path_on_root(PCH_DEVFN_UFS);
-	if (!dev)
-		params->ScsUfsEnabled = 0;
-	else
-		params->ScsUfsEnabled = dev->enabled;
-
    dev = pcidev_path_on_root(PCH_DEVFN_CSE_3);
    params->Heci3Enabled = is_dev_enabled(dev);
-#if !CONFIG(HECI_DISABLE_USING_SMM)
-	dev = pcidev_path_on_root(PCH_DEVFN_CSE);
-	params->Heci1Disabled = !is_dev_enabled(dev);
-#endif
+
    params->Device4Enable = config->Device4Enable;

/* Teton Glacier hybrid storage support */
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 2bb3024..1f07ee8 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -5,6 +5,7 @@
 #include <device/pci.h>
 #include <cpu/x86/msr.h>
 #include <console/console.h>
+#include <device/devenmap.h>
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/pmclib.h>
@@ -27,6 +28,15 @@
    unsigned int i;
    uint32_t mask = 0;

+	const struct device_enable_map devmap[] = {
+		{ &m_cfg->PchIshEnable,	PCH_DEVFN_ISH },
+		{ &m_cfg->PchHdaEnable,	PCH_DEVFN_HDA },
+		{ &m_cfg->SaIpuEnable,	SA_DEVFN_IPU },
+		{ &m_cfg->SmbusEnable,	PCH_DEVFN_SMBUS },
+	};
+
+	set_dev_state_by_devicetree(devmap, ARRAY_SIZE(devmap));
+
    /*
     * Probe for no IGD and disable InternalGfx and panel power to prevent a
     * crash in FSP-M.
@@ -88,26 +98,6 @@
    	m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
    }

-	dev = pcidev_path_on_root(PCH_DEVFN_ISH);
-	/* If ISH is enabled, enable ISH elements */
-	if (!dev)
-		m_cfg->PchIshEnable = 0;
-	else
-		m_cfg->PchIshEnable = dev->enabled;
-
-	/* If HDA is enabled, enable HDA elements */
-	dev = pcidev_path_on_root(PCH_DEVFN_HDA);
-	if (!dev)
-		m_cfg->PchHdaEnable = 0;
-	else
-		m_cfg->PchHdaEnable = dev->enabled;
-
-	/* Enable IPU only if the device is enabled */
-	m_cfg->SaIpuEnable = 0;
-	dev = pcidev_path_on_root(SA_DEVFN_IPU);
-	if (dev)
-		m_cfg->SaIpuEnable = dev->enabled;
-
    /* SATA Gen3 strength */
    for (i = 0; i < SOC_INTEL_CML_SATA_DEV_MAX; i++) {
    	if (config->sata_port[i].RxGen3EqBoostMagEnable) {
@@ -134,13 +124,6 @@
    	tconfig->DisableHeciRetry = config->DisableHeciRetry;
 #endif

-	/* Enable SMBus controller based on config */
-	dev = pcidev_path_on_root(PCH_DEVFN_SMBUS);
-	if (!dev)
-		m_cfg->SmbusEnable = 0;
-	else
-		m_cfg->SmbusEnable = dev->enabled;
-
    /* Set debug probe type */
    m_cfg->PlatformDebugConsent =
    	CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT;