Change in coreboot[master]: soc/amd/cezanne: add downcoring and SMT disable settings to devicetree

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Paul Menzel.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52197 )

Change subject: soc/amd/cezanne: add downcoring and SMT disable settings to devicetree
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Patch Set 3:

(1 comment)

File src/soc/amd/cezanne/chip.h:

https://review.coreboot.org/c/coreboot/+/52197/comment/22127daf_7ae4d890 
PS1, Line 16: disable_smt
> Ah, T vs P :) Can we add a comment that says single vs multi threads?

i added to the comment on downcore_mode that it's about physical cores; that in combination with the other option being disable_smt should be unambiguous. at least i'd say so