HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36464 )
Change subject: nb/i945: Use defined DEFAULT_RCBA ......................................................................
nb/i945: Use defined DEFAULT_RCBA
Change-Id: I166dd3edb50699dfca7b60b83cfcae996ced90dc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/acpi/i945.asl 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36464/1
diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 7a9715c..73ff17b 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -16,6 +16,7 @@
#include "hostbridge.asl" #include "../i945.h" +#include "src/southbridge/intel/common/rcba.h"
/* Operating System Capabilities Method */ Method (_OSC, 4) @@ -51,7 +52,7 @@ //})
Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36464
to look at the new patch set (#2).
Change subject: nb/i945: Use defined DEFAULT_RCBA ......................................................................
nb/i945: Use defined DEFAULT_RCBA
Change-Id: I166dd3edb50699dfca7b60b83cfcae996ced90dc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/acpi/i945.asl 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36464/2
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36464
to look at the new patch set (#3).
Change subject: nb/i945: Use defined DEFAULT_RCBA ......................................................................
nb/i945: Use defined DEFAULT_RCBA
Change-Id: I166dd3edb50699dfca7b60b83cfcae996ced90dc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/acpi/i945.asl 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36464/3
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36464
to look at the new patch set (#4).
Change subject: nb/intel: Use defined DEFAULT_RCBA ......................................................................
nb/intel: Use defined DEFAULT_RCBA
Change-Id: I166dd3edb50699dfca7b60b83cfcae996ced90dc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/i945/acpi/i945.asl M src/northbridge/intel/nehalem/acpi/nehalem.asl M src/northbridge/intel/pineview/acpi/pineview.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl 6 files changed, 12 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36464/4
Hello Patrick Rudolph, Arthur Heymans, build bot (Jenkins), Nico Huber, Damien Zammit,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36464
to look at the new patch set (#5).
Change subject: nb/intel: Use defined DEFAULT_RCBA ......................................................................
nb/intel: Use defined DEFAULT_RCBA
Change-Id: I166dd3edb50699dfca7b60b83cfcae996ced90dc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/i945/acpi/i945.asl M src/northbridge/intel/nehalem/acpi/nehalem.asl M src/northbridge/intel/pineview/acpi/pineview.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl M src/northbridge/intel/x4x/acpi/x4x.asl 7 files changed, 14 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36464/5
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36464 )
Change subject: nb/intel: Use defined DEFAULT_RCBA ......................................................................
Patch Set 5: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36464 )
Change subject: nb/intel: Use defined DEFAULT_RCBA ......................................................................
nb/intel: Use defined DEFAULT_RCBA
Change-Id: I166dd3edb50699dfca7b60b83cfcae996ced90dc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/36464 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/i945/acpi/i945.asl M src/northbridge/intel/nehalem/acpi/nehalem.asl M src/northbridge/intel/pineview/acpi/pineview.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl M src/northbridge/intel/x4x/acpi/x4x.asl 7 files changed, 14 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 4678e1f..a3f9e90 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -16,6 +16,7 @@
#include "hostbridge.asl" #include "../gm45.h" +#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ Device (PDRC) @@ -36,7 +37,7 @@ //})
Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 0f0d383..45ebff2 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -16,6 +16,7 @@
#include "../haswell.h" #include "hostbridge.asl" +#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ Device (PDRC) @@ -24,7 +25,7 @@ Name (_UID, 1)
Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 7a9715c..50fabdc 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -16,6 +16,7 @@
#include "hostbridge.asl" #include "../i945.h" +#include <southbridge/intel/common/rcba.h>
/* Operating System Capabilities Method */ Method (_OSC, 4) @@ -51,7 +52,7 @@ //})
Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl index df8aad7..404801e 100644 --- a/src/northbridge/intel/nehalem/acpi/nehalem.asl +++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl @@ -16,6 +16,7 @@
#include "../nehalem.h" #include "hostbridge.asl" +#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ Device (PDRC) @@ -24,7 +25,7 @@ Name (_UID, 1)
Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 72f97e4..c7602e1 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -16,6 +16,7 @@
#include "hostbridge.asl" #include "../iomap.h" +#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ Device (PDRC) @@ -28,7 +29,7 @@ */
Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) /* RCBA */ + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 7fdfe42..3181fc0 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -17,6 +17,7 @@
#include "hostbridge.asl" #include "peg.asl" +#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ Device (PDRC) @@ -25,7 +26,7 @@ Name (_UID, 1)
Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) // Filled by _CRS Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB) Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB) diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 8458db3..a486808 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -17,6 +17,7 @@
#include "hostbridge.asl" #include "../iomap.h" +#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ Device (PDRC) @@ -25,7 +26,7 @@ Name (_UID, 1)
Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)