[S] Change in coreboot[master]: mb/google/skyrim/var/frostflow: Update DPTC and STT settings

[Tim Van Patten (Code Review)]

Attention is currently required from: Frank Wu, John Su, Dtrain Hsu, Jason Nien, Jon Murphy, Chris Wang, Martin Roth, Karthik Ramasubramanian.

Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73081 )

Change subject: mb/google/skyrim/var/frostflow: Update DPTC and STT settings
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Patch Set 4:

(1 comment)

File src/mainboard/google/skyrim/variants/frostflow/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/73081/comment/66a9d94b_6268dde3 
PS4, Line 159: 	register "stt_alpha_apu" = "0x4ccd"
             : 	register "stt_error_coeff" = "0x21"
             : 	register "stt_error_rate_coefficient" = "0x2666"
These values are not being set in `src/third_party/coreboot/src/soc/amd/mendocino/root_complex.c`.

They need to be added to `src/third_party/coreboot/src/soc/amd/common/block/include/amdblocks/alib.h` and the macro `DPTC_INPUTS`. AMD doc #55483 has the offset values.

Default vaules will need to be added  to `src/third_party/coreboot/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb`, so every board has them set by `DPTC_INPUTS`.