[S] Change in coreboot[master]: soc/amd/common/blk/pcie: Program LTR max latencies

[Matt DeVillier (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Eric Lai, Martin Roth, Fred Reitberger, Felix Held.

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74288 )

Change subject: soc/amd/common/blk/pcie: Program LTR max latencies
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Patch Set 3:

(1 comment)

File src/soc/amd/common/block/pci/pcie_gpp.c:

https://review.coreboot.org/c/coreboot/+/74288/comment/d6f03232_5b3ddc86 
PS1, Line 51: PCIE_LTR_MAX_LATENCY_1047US
> IMHO Kconfig provides the flexibility for future change. But I am fine either way.

or, the SoC can override the common value at the SoC level, just like Intel is doing :)