[M] Change in coreboot[main]: soc/amd/glinda/cpu: Update cache info

[Naresh Solanki (Code Review)]

Attention is currently required from: Angel Pons, Jérémy Compostella.

Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email )

Change subject: soc/amd/glinda/cpu: Update cache info
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Patch Set 3:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/85640/comment/fbd41f9f_e21820d3?usp... :
PS3, Line 8:
> Could you please describe why this had to be updated? I'm not familiar with the cache hierarchy on t […]

Previously Cache size of only BSP was reported.
In case of Glinda, L3 caches is 16 + 8 shared between Classic & Dense cores.
Thus requiring alternate approach to identify cache size.

File src/soc/amd/glinda/cpu.c:

https://review.coreboot.org/c/coreboot/+/85640/comment/ada77794_48b4fa66?usp... :
PS3, Line 66: 	memcpy(info, &info_list[0], sizeof(*info));
> Out of curiosity, is this copy necessary?

This part may need some optimisation. The caller expect data for as part of struct info.
Here we take this as sample from info_list[0] & manupalate size based on id so that as end result, smbios reports right amount of cache size.