[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PLL and Clock init support

[Yidi Lin (Code Review)]

Attention is currently required from: Guangjie Song, Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu.

Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84495?usp=email )

Change subject: soc/mediatek/mt8196: Add PLL and Clock init support
......................................................................

Patch Set 26:

(2 comments)

File src/soc/mediatek/mt8196/pll.c:

https://review.coreboot.org/c/coreboot/+/84495/comment/ebf3f828_293d31f5?usp... :
PS13, Line 1196: 30
> Alternatively, most of the `mtcmos_idx` values are `PM_DUMMY1`. Can we store only the two entries […]

Agree with Yu-Ping. We can default set `cg_idx` 0 ~ 49 to`PM_DUMMY1` and subsequently set above two entries.

File src/soc/mediatek/mt8196/pll.c:

https://review.coreboot.org/c/coreboot/+/84495/comment/8e2b1ba3_7e8d5bc8?usp... :
PS26, Line 1176: mmvote_mtcmos_mtcmos_table
`child_idx` is the same as `parent_idx`. Is is expected ? Can we just keep either one ?