Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 )
Change subject: [WIP] mb/acer: Add Acer Aspire ES1-572 ......................................................................
Patch Set 9:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... File src/mainboard/acer/es1-572/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 40: register "SataPortsDevSlp[0]" = "0" : register "SataPortsDevSlp[1]" = "0" :
the latter part is exactly why I've left these here.
schematics say nooooo ;)
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 42: SataSpeedLimit" = "3" speed 3 (also matches 0) is the default already
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 108: device pci 04.0 off end # CPU Thermal Subsystem
why on? […]
it's not about EC ACPI and it's not only about DPTF. device 4 also gets used by linux to read/set TCC and for rapl power limits
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... File src/mainboard/acer/es1-572/romstage.c:
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 32: /* These settings are most likely useless if using a release build of FSP */ : mem_cfg->PcdDebugInterfaceFlags = 2; /* 2: Enable UART */ : mem_cfg->PcdSerialIoUartNumber = 2; /* 2: Use UART #2 */ : mem_cfg->PcdSerialDebugBaudRate = 7; /* 7: 115200 baud */ : mem_cfg->PcdSerialDebugLevel = 3; /* 3: Log <= Info */ : well, that's all fsp defaults (except the TH bit in PcdSerialIoUartNumber, which doesn't do anything with TH disabled)
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Michael Niewöhner (Code Review)