Change in coreboot[master]: soc/intel/alderlake: Determine PCIe RP enable mask using device on/of...
EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status
This change uses the newly added helper function `pcie_rp_enable_mask()` to determine the mask of PCH and CPU PCIe root ports that are enabled by the mainboard instead of relying on PcieRpEnable[] config.
Since pch_lp_rp_groups are used by more than just chip.c, this change also adds pcie_rp.c that provides a helper function to get the PCIe RP group table for the PCH.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.c A src/soc/intel/alderlake/include/soc/pcie.h A src/soc/intel/alderlake/pcie_rp.c 4 files changed, 43 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/49021/1
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index d962b75..f31cf98 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += espi.c romstage-y += gpio.c romstage-y += meminit.c +romstage-y += pcie_rp.c romstage-y += reset.c
ramstage-y += acpi.c @@ -38,6 +39,7 @@ ramstage-y += lockdown.c ramstage-y += me.c ramstage-y += p2sb.c +ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += smmrelocate.c diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 794c3ba..67cfe32 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -13,15 +13,10 @@ #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/ramstage.h> #include <soc/soc_chip.h>
-static const struct pcie_rp_group pch_lp_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, - { 0 } -}; - #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -149,7 +144,7 @@ soc_fill_gpio_pm_configuration();
/* Swap enabled PCI ports in device tree if needed. */ - pcie_rp_update_devicetree(pch_lp_rp_groups); + pcie_rp_update_devicetree(get_pch_pcie_rp_table()); }
static struct device_operations pci_domain_ops = { diff --git a/src/soc/intel/alderlake/include/soc/pcie.h b/src/soc/intel/alderlake/include/soc/pcie.h new file mode 100644 index 0000000..effc8e2 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/pcie.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_ALDERLAKE_PCIE_H__ +#define __SOC_ALDERLAKE_PCIE_H__ + +#include <intelblocks/pcie_rp.h> + +const struct pcie_rp_group *get_pch_pcie_rp_table(void); +const struct pcie_rp_group *get_cpu_pcie_rp_table(void); + +#endif /* __SOC_ALDERLAKE_PCIE_H__ */ + diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c new file mode 100644 index 0000000..de7e015 --- /dev/null +++ b/src/soc/intel/alderlake/pcie_rp.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/pcie_rp.h> +#include <soc/pci_devs.h> +#include <soc/pcie.h> + +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, + { 0 } +}; + +const struct pcie_rp_group *get_pch_pcie_rp_table(void) +{ + return pch_lp_rp_groups; +} + +/* TODO check how to determine CPU PCIE port */ +static const struct pcie_rp_group cpu_rp_groups[] = { + { .slot = SA_DEV_SLOT_CPU_PCIE, .count = 1 }, + { 0 } +}; + +const struct pcie_rp_group *get_cpu_pcie_rp_table(void) +{ + return cpu_rp_groups; +}
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49021
to look at the new patch set (#2).
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status
This change uses the newly added helper function `pcie_rp_enable_mask()` to determine the mask of PCH and CPU PCIe root ports that are enabled by the mainboard instead of relying on PcieRpEnable[] config.
Since pch_lp_rp_groups are used by more than just chip.c, this change also adds pcie_rp.c that provides a helper function to get the PCIe RP group table for the PCH.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.c A src/soc/intel/alderlake/include/soc/pcie.h A src/soc/intel/alderlake/pcie_rp.c 4 files changed, 42 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/49021/2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49021/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/49021/2//COMMIT_MSG@9 PS2, Line 9: This change uses the newly added helper function : `pcie_rp_enable_mask()` to determine the mask of PCH and CPU PCIe root : ports that are enabled by the mainboard instead of relying on : PcieRpEnable[] config. : where is that? I don't see it in this change
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49021/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/49021/2//COMMIT_MSG@9 PS2, Line 9: This change uses the newly added helper function : `pcie_rp_enable_mask()` to determine the mask of PCH and CPU PCIe root : ports that are enabled by the mainboard instead of relying on : PcieRpEnable[] config. :
where is that? I don't see it in this change
This CL is in the related chain.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49021/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/49021/2//COMMIT_MSG@9 PS2, Line 9: This change uses the newly added helper function : `pcie_rp_enable_mask()` to determine the mask of PCH and CPU PCIe root : ports that are enabled by the mainboard instead of relying on : PcieRpEnable[] config. :
This CL is in the related chain.
eh, yes, but the commit message describes the commit, not the chain
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
Patch Set 2:
(1 comment)
Will change the commit message later with new patch after :)
https://review.coreboot.org/c/coreboot/+/49021/2/src/soc/intel/alderlake/pci... File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/2/src/soc/intel/alderlake/pci... PS2, Line 18: /* TODO check how to determine CPU PCIE port */ From ADL EDS, need to check 01.0, 06.0 and 06.2... need to work out how to deal with it here.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49021/2/src/soc/intel/alderlake/pci... File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/2/src/soc/intel/alderlake/pci... PS2, Line 18: /* TODO check how to determine CPU PCIE port */
From ADL EDS, need to check 01.0, 06.0 and 06.2... need to work out how to deal with it here.
We need to understand how each logical PCI device maps to the CpuPcieRpEnable UPD, the help text isn't helpful: ``` Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. ```
I'd guess it's gen5 port is bit 0, gen 4 port 1 is bit 1, gen 4 port 2 is bit 2, but IDK
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49021/2/src/soc/intel/alderlake/pci... File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/2/src/soc/intel/alderlake/pci... PS2, Line 18: /* TODO check how to determine CPU PCIE port */
We need to understand how each logical PCI device maps to the CpuPcieRpEnable UPD, the help text isn […]
Yes, I asked Subrata, but no respond.. sad. Maybe create an issue for it?
Attention is currently required from: EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/a6ea399a_82656bfa PS2, Line 18: /* TODO check how to determine CPU PCIE port */
Yes, I asked Subrata, but no respond.. sad. […]
Verified this, it's:
bit 0 = 00:06.0 bit 1 = 00:01.0 bit 2 = 00:06.2
Attention is currently required from: Tim Wawrzynczak, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/ce0ae1e1_19e6837d PS2, Line 18: /* TODO check how to determine CPU PCIE port */
Verified this, it's: […]
Tim is right here, sorry for my delated response
Attention is currently required from: Tim Wawrzynczak. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2: okay, let's wait Furquan change the patch for noncontinuous CPU RP. And I will submit new patch :p
Attention is currently required from: Tim Wawrzynczak, Subrata Banik, EricR Lai. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/04fd2bd6_94c2bd44 PS2, Line 18: /* TODO check how to determine CPU PCIE port */
Tim is right here, sorry for my delated response
If the indexes match the port numbers in the link capabilities (they do on the PCH, off-by-one), we could read them from the config space. cf. src/soc/intel/common/block/pcie/pcie_rp.c:33
The EDS says they are RO/V, though (can be changed by hardware). If that really is the case, and FSP uses a static mapping, it wouldn't work.
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/139881e0_78ad7552 PS2, Line 18: /* TODO check how to determine CPU PCIE port */
If the indexes match the port numbers in the link capabilities […]
This won't be a problem here. Furquan will change the helper and group like below. You can refer the comment in his CL.
struct pcie_rp_group {
unsigned int slot; unsigned int start; unsigned int count; }; This will allow SoC to define a group such that even non-contiguous functions can be allowed:
struct pcie_rp_group cpu_p_rp_groups[] = {
{ .slot = PCH_DEV_SLOT_CPU_6, .start = 0, .count = 1, }, { .slot = PCH_DEV_SLOT_CPU_1, .start = 0, .count = 1, }, { .slot = PCH_DEV_SLOT_CPU_6, .start = 2, .count = 1, }, };
Attention is currently required from: Tim Wawrzynczak, Subrata Banik, EricR Lai. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/d5a620cf_fd39f2a3 PS2, Line 18: /* TODO check how to determine CPU PCIE port */
This won't be a problem here. Furquan will change the helper and group like below. […]
That would work, but it doesn't solve "the" problem. We'd have to keep the undocumented blob and coreboot in sync.
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/1d5ad46c_39e5e577 PS2, Line 18: /* TODO check how to determine CPU PCIE port */
That would work, but it doesn't solve "the" problem. We'd have to keep […]
Yes... But coreboot dosen't care FSP at all. We don't know how FSP remap or configure the UPD. I ask for this many times. Anyway this is Intel can do better after.
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49021
to look at the new patch set (#3).
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
soc/intel/alderlake: Update PCH and CPU PCIe RP table
According ADL EDS to update the PCH and CPU PCIe RP table.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/include/soc/pci_devs.h A src/soc/intel/alderlake/include/soc/pcie.h A src/soc/intel/alderlake/pcie_rp.c 5 files changed, 48 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/49021/3
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49021/comment/583ee047_137caf15 PS2, Line 9: This change uses the newly added helper function : `pcie_rp_enable_mask()` to determine the mask of PCH and CPU PCIe root : ports that are enabled by the mainboard instead of relying on : PcieRpEnable[] config. :
eh, yes, but the commit message describes the commit, not the chain
Done
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/49021/comment/4960ce82_0e64391c PS3, Line 41: #define SA_DEVFN_CPU_PCIE6 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 0) #define SA_DEVFN_CPU_PCIE6_0 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 0) #define SA_DEVFN_CPU_PCIE6_2 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 2)
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/49021/comment/3de806b9_7250a17b PS3, Line 41: #define SA_DEVFN_CPU_PCIE6 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 0)
#define SA_DEVFN_CPU_PCIE6_0 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 0) […]
okay let me change PCIE1 as well.
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49021
to look at the new patch set (#4).
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
soc/intel/alderlake: Update PCH and CPU PCIe RP table
According ADL EDS to update the PCH and CPU PCIe RP table.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/include/soc/pci_devs.h A src/soc/intel/alderlake/include/soc/pcie.h A src/soc/intel/alderlake/pcie_rp.c 5 files changed, 49 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/49021/4
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4: @Eric, can i request you to add Hashtags like this "NEED_ADLRVP_TEST" so i can ask sometime ADLRVP team to verify those CLs and ensure no issue.
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
@Eric, can i request you to add Hashtags like this "NEED_ADLRVP_TEST" so i can ask sometime ADLRVP t […]
Sure, but need wait Furquan patch to fix the CPU_RP noncontinuous.
Attention is currently required from: Nico Huber, Subrata Banik, Michael Niewöhner, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 4:
(2 comments)
File src/soc/intel/alderlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/49021/comment/4c91d855_dc0d5b0e PS4, Line 25: PCH SA
https://review.coreboot.org/c/coreboot/+/49021/comment/f1d86263_af8f423d PS4, Line 40: PCH SA
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/d5d3138e_ea1c5d89 PS2, Line 18: /* TODO check how to determine CPU PCIE port */
If the indexes match the port numbers in the link capabilities
(they do on the PCH, off-by-one), we could read them from the config space.
It is not clear from the documentation how the ports are numbered in the link capabilities. Probably someone with access to the hardware can play with this to get a better understanding. EDS says 01h for both 0/1/0 as well as 0/6/*.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 4:
(2 comments)
File src/soc/intel/alderlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/49021/comment/88eb2745_0e2126fd PS4, Line 40: PCH
SA
Done
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/51444602_f03ead01 PS2, Line 18: /* TODO check how to determine CPU PCIE port */
If the indexes match the port numbers in the link capabilities […]
wait for your new patch, I leave TODO here.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49021
to look at the new patch set (#5).
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
soc/intel/alderlake: Update PCH and CPU PCIe RP table
According ADL EDS to update the PCH and CPU PCIe RP table.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/include/soc/pci_devs.h A src/soc/intel/alderlake/include/soc/pcie.h A src/soc/intel/alderlake/pcie_rp.c 5 files changed, 49 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/49021/5
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49021
to look at the new patch set (#6).
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
soc/intel/alderlake: Update PCH and CPU PCIe RP table
According ADL EDS to update the PCH and CPU PCIe RP table.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/include/soc/pci_devs.h A src/soc/intel/alderlake/include/soc/pcie.h A src/soc/intel/alderlake/pcie_rp.c 5 files changed, 49 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/49021/6
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/alderlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/49021/comment/968dec08_970f8630 PS4, Line 25: PCH
SA
Done
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
Patchset:
PS6: should we wait for the CL to fixup the non-contiguous pcie slots?
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/adce2e05_abb4e907 PS2, Line 18: /* TODO check how to determine CPU PCIE port */
wait for your new patch, I leave TODO here.
Pushed change here: https://review.coreboot.org/c/coreboot/+/49370
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49021
to look at the new patch set (#7).
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
soc/intel/alderlake: Update PCH and CPU PCIe RP table
According ADL EDS to update the PCH and CPU PCIe RP table.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/include/soc/pci_devs.h A src/soc/intel/alderlake/include/soc/pcie.h A src/soc/intel/alderlake/pcie_rp.c 5 files changed, 49 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/49021/7
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/57846814_442e8b71 PS7, Line 18: /* TODO wait pcie_rp_group change for uncontinuous slot */ forgot remove this..
Attention is currently required from: Nico Huber, Subrata Banik, Michael Niewöhner, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 7: Code-Review+1
(1 comment)
Patchset:
PS7: looks good with the comment removed
Attention is currently required from: Nico Huber, Subrata Banik, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49021
to look at the new patch set (#8).
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
soc/intel/alderlake: Update PCH and CPU PCIe RP table
According ADL EDS to update the PCH and CPU PCIe RP table.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/include/soc/pci_devs.h A src/soc/intel/alderlake/include/soc/pcie.h A src/soc/intel/alderlake/pcie_rp.c 5 files changed, 48 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/49021/8
Attention is currently required from: Nico Huber, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/936413c2_79acb9ee PS7, Line 18: /* TODO wait pcie_rp_group change for uncontinuous slot */
forgot remove this..
Done
Attention is currently required from: Nico Huber, Subrata Banik, Michael Niewöhner, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 8: Code-Review+2
Attention is currently required from: Nico Huber, Subrata Banik, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 8:
(2 comments)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/b84c252a_c5da20f7 PS8, Line 18: static const struct pcie_rp_group cpu_rp_groups[] = { Can you please add a comment here indicating that this order is basically aligned with FSP expectations for the CPU PCIe UPD?
https://review.coreboot.org/c/coreboot/+/49021/comment/d998634a_5b42e478 PS8, Line 21: { .slot = SA_DEV_SLOT_CPU_6, .start = 2, .count = 1 }, This table needs to end with { 0 }.
Attention is currently required from: Nico Huber, Subrata Banik, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49021
to look at the new patch set (#9).
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
soc/intel/alderlake: Update PCH and CPU PCIe RP table
According ADL EDS to update the PCH and CPU PCIe RP table.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/include/soc/pci_devs.h A src/soc/intel/alderlake/include/soc/pcie.h A src/soc/intel/alderlake/pcie_rp.c 5 files changed, 55 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/49021/9
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 8:
(2 comments)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/12af5361_01539a5a PS8, Line 18: static const struct pcie_rp_group cpu_rp_groups[] = {
Can you please add a comment here indicating that this order is basically aligned with FSP expectati […]
Done
https://review.coreboot.org/c/coreboot/+/49021/comment/1242c8b0_d28f5322 PS8, Line 21: { .slot = SA_DEV_SLOT_CPU_6, .start = 2, .count = 1 },
This table needs to end with { 0 }.
Done
Attention is currently required from: Nico Huber, Subrata Banik, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 9: Code-Review+2
(2 comments)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/3327fe43_74abff9a PS8, Line 18: static const struct pcie_rp_group cpu_rp_groups[] = {
Done
Thanks Eric!
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/3cafcf03_217516ea PS9, Line 20: SSD1 I don't think we need to mention SSD1 / SSD2 here since it is mainboard-dependent.
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/210e9380_aef20445 PS9, Line 20: SSD1
I don't think we need to mention SSD1 / SSD2 here since it is mainboard-dependent.
How about x4 CPU Slot?
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49021
to look at the new patch set (#10).
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
soc/intel/alderlake: Update PCH and CPU PCIe RP table
According ADL EDS to update the PCH and CPU PCIe RP table.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/include/soc/pci_devs.h A src/soc/intel/alderlake/include/soc/pcie.h A src/soc/intel/alderlake/pcie_rp.c 5 files changed, 55 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/49021/10
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/alderlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/49021/comment/5196201c_49435144 PS9, Line 20: SSD1
How about x4 CPU Slot?
Done
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 11: Code-Review+2
Attention is currently required from: Nico Huber, Subrata Banik, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
Patch Set 11: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table ......................................................................
soc/intel/alderlake: Update PCH and CPU PCIe RP table
According ADL EDS to update the PCH and CPU PCIe RP table.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/include/soc/pci_devs.h A src/soc/intel/alderlake/include/soc/pcie.h A src/soc/intel/alderlake/pcie_rp.c 5 files changed, 55 insertions(+), 9 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index d962b75..f31cf98 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += espi.c romstage-y += gpio.c romstage-y += meminit.c +romstage-y += pcie_rp.c romstage-y += reset.c
ramstage-y += acpi.c @@ -38,6 +39,7 @@ ramstage-y += lockdown.c ramstage-y += me.c ramstage-y += p2sb.c +ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += smmrelocate.c diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 95b6b8f..c7e3fb8 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -14,15 +14,10 @@ #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/ramstage.h> #include <soc/soc_chip.h>
-static const struct pcie_rp_group pch_lp_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, - { 0 } -}; - #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -150,7 +145,7 @@ soc_fill_gpio_pm_configuration();
/* Swap enabled PCI ports in device tree if needed. */ - pcie_rp_update_devicetree(pch_lp_rp_groups); + pcie_rp_update_devicetree(get_pch_pcie_rp_table()); }
static struct device_operations pci_domain_ops = { diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index d86e81d..098c31d 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -22,6 +22,9 @@ #define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) #endif
+#define SA_DEV_SLOT_CPU_1 0x01 +#define SA_DEVFN_CPU_PCIE1_0 PCI_DEVFN(PCH_DEV_SLOT_CPU_1, 0) + #define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) @@ -34,8 +37,9 @@ #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) #define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
-#define SA_DEV_SLOT_CPU_PCIE 0x06 -#define SA_DEVFN_CPU_PCIE PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0) +#define SA_DEV_SLOT_CPU_6 0x06 +#define SA_DEVFN_CPU_PCIE6_0 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 0) +#define SA_DEVFN_CPU_PCIE6_2 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 2)
#define SA_DEV_SLOT_TBT 0x07 #define SA_DEVFN_TBT(x) PCI_DEVFN(SA_DEV_SLOT_TBT, (x)) diff --git a/src/soc/intel/alderlake/include/soc/pcie.h b/src/soc/intel/alderlake/include/soc/pcie.h new file mode 100644 index 0000000..cd76d09 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/pcie.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_ALDERLAKE_PCIE_H__ +#define __SOC_ALDERLAKE_PCIE_H__ + +#include <intelblocks/pcie_rp.h> + +const struct pcie_rp_group *get_pch_pcie_rp_table(void); +const struct pcie_rp_group *get_cpu_pcie_rp_table(void); + +#endif /* __SOC_ALDERLAKE_PCIE_H__ */ diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c new file mode 100644 index 0000000..4ec24c2 --- /dev/null +++ b/src/soc/intel/alderlake/pcie_rp.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/pcie_rp.h> +#include <soc/pci_devs.h> +#include <soc/pcie.h> + +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, + { 0 } +}; + +const struct pcie_rp_group *get_pch_pcie_rp_table(void) +{ + return pch_lp_rp_groups; +} + +/* + * ADL-P FSP define CPU RP as below: + * RP1: PEG60 : 0:6:0 : x4 CPU Slot + * RP2: PEG10 : 0:1:0 : x8 CPU Slot + * RP3: PEG62 : 0:6:2 : x4 CPU Slot + */ +static const struct pcie_rp_group cpu_rp_groups[] = { + { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1 }, + { .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 1 }, + { .slot = SA_DEV_SLOT_CPU_6, .start = 2, .count = 1 }, + { 0 } +}; + +const struct pcie_rp_group *get_cpu_pcie_rp_table(void) +{ + return cpu_rp_groups; +}
-
EricR Lai (Code Review) -
Furquan Shaikh (Code Review)
-
Michael Niewöhner (Code Review)
-
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)
-
Subrata Banik (Code Review)
-
Tim Wawrzynczak (Code Review)